Current mode analog-to-digital converter (ADC)
AssigneeRockwell Collins, Inc.
InventorsWenlu Chen, Han Chi Hsieh, Raymond Zanoni
Life of this patent
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Abstract
A current-mode analog-digital conversion (ADC) circuit directly samples and digitizes an input signal in the current domain; the input signal may be a current signal or a photonic signal. Input capacitors may be coupled to the current source by a series of switches and configured to store a target charge. The target charge may be compared to a reference voltage by comparators of the system to generate digital output. The current-mode ADC circuit may be adapted to flash, successive-approximation, and pipeline architectures, or embodied in a photonic receiver incorporating current-mode ADC circuits configured to sample and digitize photonic signals.
Claims20
A successive-approximation current-mode analog-digital converter (ADC), comprising:
- at least one input capacitor configured to store a target charge by sampling a current-mode input signal from a current source via an interleaving switch, the at least one input capacitor including an array of at least N capacitors coupled to the current source via a common terminal, where N is an integer;
- at least one comparator coupled to the at least one input capacitor, the at least one comparator configured to generate at least one N-bit digital output signal by comparing a target voltage to a reference voltage, the target voltage corresponding to the target charge;
- and
- at least one reset switch coupled to the current source, the reset switch configured to release the target charge.
An interleaving current-mode ADC, comprising:
- at least one input capacitor configured to store a target charge by sampling a current-mode input signal via at least one interleaving switch coupled to a current source;
- at least one comparator coupled to the at least one input capacitor, the at least one comparator configured to generate at least one digital output signal by comparing a target voltage to a reference voltage, the target voltage corresponding to the target charge;
- and
- at least one reset switch coupled to the current source and to the interleaving switch, the reset switch configured to release the target charge.
A method for current-mode analog-digital conversion, the method comprising:
- closing at least one interleaving switch coupled to a current source and an input capacitor;
- opening at least one reset switch coupled to the input capacitor and the current source;
- storing at least one target charge to the input capacitor by sampling in a current domain at least one input signal received from the current source via the at least one interleaving switch;
- generating, via at least one comparator, at least one digital output signal by comparing at least one reference voltage to a target voltage corresponding to the at least one target charge;
- and
- releasing the at least one target charge by closing the at least one reset switch.
A pipeline current-mode analog-digital converter (ADC), comprising:
- at least one input capacitor configured to store a target charge by sampling a current-mode input signal from a current source via an interleaving switch;
- at least one comparator coupled to the at least one input capacitor, the at least one comparator configured to generate at least one digital output signal by comparing a target voltage to a reference voltage, the target voltage corresponding to the target charge;
- at least one reset switch coupled to the current source, the reset switch configured to release the target charge;
- a sequence of at least P Q-bit stages, where P and Q are integers, each stage configured to:
- receive the current-mode input signal from at least one of the current source and the preceding stage;
- and
- generate at least one Q-bit digital output based on the received current mode input signal;
- a plurality of shift registers coupled to the sequence of stages and configured to time-align the sequence of Q-bit digital outputs;
- and
- digital error-correction logic coupled to the plurality of shift registers and configured to generate at least one Q-bit digital output signal based on the sequence of time-aligned Q-bit digital outputs.
Dependencies are inferred from the claim text.