Spread spectrum clocking phase error cancellation for analog CDR/PLL

A method for generating a local clock from a clock reference signal, the method comprising:

• forming a phase error signal proportional to a difference between a phase of the clock reference signal and a phase of an output of a voltage controlled oscillator;
• forming a current, from a charge pump, proportional to the phase error signal;
• forming an offset current by:
• estimating an amplitude and estimating a phase of a square wave signal proportional to a time derivative of a triangle wave frequency modulation in the clock reference signal;
• generating a square wave signal having the amplitude and phase;
• and
• providing the square wave signal to a current digital to analog converter;
• adding the offset current to the current from the charge pump to form a total current;
• and
• filtering the total current with a loop filter to form a control signal for the voltage controlled oscillator.

A display comprising:

• a transmitter to transmit digital data and a clock reference signal;
• and
• a receiver,
• the receiver comprising
• a phase locked loop;
• and
• a phase error reducing circuit comprising:
• a timing estimation circuit to estimate a phase of a square wave offsetting signal for offsetting an effect of a triangle wave frequency modulation in the clock reference signal;
• an amplitude estimation circuit to estimate an amplitude of the offsetting signal, and for generating the offsetting signal;
• and
• an offset injection circuit to inject the offsetting signal into the phase locked loop,
• the phase error reducing circuit being for reducing the effect of the frequency modulation on a phase error of the phase locked loop.