Hum generation using representative circuitry
AssigneeWave Computing, Inc.
InventorsGajendra Prasad Singh, Shaishav Desai
Life of this patent
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Abstract
Disclosed embodiments select a proper hum frequency reference by utilizing one or more functional logic circuits within a cluster. The slowest logic circuit is determined, and an instance of that logic circuit is used in timing circuitry for the cluster. Multiple logic circuits with similar characteristics are incorporated into the timing circuit. Each cluster is interconnected to a second level timing circuit. Each cluster inputs timing information into the second level timing circuit. The second level timing circuit then determines when the next cycle, or tic, of the self-generated clock starts, and the process repeats, providing a self-generated clock signal.
Claims19
An apparatus for signal generation comprising:
- a first plurality of representative logic circuits;
- a first edge aligner combining results from the first plurality of representative logic circuits;
- a first enablement circuit that enables the first plurality of representative logic circuits;
- a first synchronization signal derived from the results from the first plurality of representative logic circuits;
- a second plurality of representative logic circuits;
- a second edge aligner combining results from the second plurality of representative logic circuits;
- a second enablement circuit that enables the second plurality of representative logic circuits;
- a second synchronization signal derived from the results from the second plurality of representative logic circuits;
- and
- a combined synchronization signal derived from the first synchronization signal and the second synchronization signal.
Dependencies are inferred from the claim text.