Semiconductor integrated circuit device regarding the detection of degradation

A semiconductor integrated circuit device comprising:

• an inverter including a target PMOS transistor coupled to a target NMOS transistor;
• a first stress-applying circuit configured to apply a first direct current (DC) level to a gate of the target PMOS transistor;
• a second stress-applying circuit configured to apply a second DC level to a gate of the target NMOS transistor;
• a third stress-applying circuit configured to apply an alternating current (AC) voltage to the gate of the target NMOS transistor in response to a target NMOS selection signal;
• and
• a fourth stress-applying circuit configured to apply the AC voltage to a drain of the target NMOS transistor, when the alternating current voltage is applied to the gate of the target NMOS transistor, in response to the target NMOS selection signal,
• wherein the fourth stress-applying circuit includes an RC delay.