Multi-level output cascode power stage

An amplifier system, comprising:

• a power stage having inputs for at least two supply voltages and an output voltage node for coupling to a load, the power stage including:
• a first plurality of transistors, at least one of the first plurality of transistors being disposed between an intermediate voltage node and the output voltage node, and at least two of the first plurality of transistors being connected in series and disposed between a high voltage node and the output voltage node;
• a second plurality of transistors being connected in a cascode configuration and disposed between the output voltage node and a low voltage node, wherein the cascode configuration provides a protective mode when at least one of the transistors of the second plurality is off;
• and
• a driver to generate control signals to the power stage that causes the power stage to vary an output voltage applied to the load from among the at least three voltage levels.

A method, comprising:

• generating an output voltage to a load, by a power stage having inputs for at least two supply voltages, the power stage including:
• a first plurality of transistors, at least one of the first plurality of transistors being disposed between an intermediate voltage node and an output voltage node, and at least two of the first plurality of transistors being connected in series and disposed between a high voltage node and the output voltage node;
• a second plurality of transistors being connected in a cascode configuration and disposed between the output voltage node and a low voltage node, wherein the cascode configuration provides a protective mode when at least one of the transistors of the second plurality is off;
• and
• generating control signals to the power stage, by a controller, to cause the power stage to vary the output voltage applied to the load from among more three voltage levels.

A multi-level output power stage, comprising:

• inputs for at least two supply voltages;
• an output voltage node for coupling to a load;
• a first plurality of transistors, at least one of the first plurality of transistors being disposed between an intermediate voltage node and the output voltage node, and at least two of the first plurality of transistors being connected in series and disposed between a high voltage node and the output voltage node;
• and
• a second plurality of transistors being connected in a cascode configuration and disposed between the output voltage node and a low voltage node, wherein the cascode configuration provides a protective mode when at least one of the transistors of the second plurality is off.