Bias circuitry for depletion mode amplifiers

#This disclosure relates generally to bias circuitry and more particularly to bias circuitry for depletion mode amplifiers.

#As is known in the art, RF power amplifiers using depletion mode transistors to amplify an input radio frequency signal often use solid state “drain” switches to turn on and off DC supply power.

#An alternative to the drain switch is the gate switch, where a sufficiently negative voltage is supplied to the power amplifier's transistor gate to reduce the DC quiescent current to zero and also provide sufficient isolation in the RF path. An advantage of the gate switch approach is faster switching times between RF enable and of for systems using RF amplifiers. One such circuit (FIG. 1) is shown in U.S. Pat. No. 6,600,301 B1, issued Jul. 29, 2003, inventor DeFalco, assigned to the same assignee as the present invention. While such circuit has been found to be effective in many applications, in applications having a wide variation in temperature and power supply, a sufficient off-state voltage must be applied to it to establish proper quiescent bias for proper RF amplifier operation inclusive of process, temperature, and power supply variations.

#FIG. 1 is a circuit according to the PRIOR ART:

#FIG. 2 is a circuit according to the disclosure;

#FIG. 3 is a circuit according to an alternative embodiment of the disclosure; and

#Like reference symbols in the various drawings indicate like elements.

#Referring now to FIG. 2, a circuit 10 is shown baying an amplifier 11, here a radio frequency (RF Amp), comprising: a depletion mode transistor Q1 having a source electrode coupled to a reference potential, here ground; a drain electrode coupled to a potential more positive than the reference potential, here (+Vdd) through an inductor L2, as shown, the drain electrode providing an amplified RF output after passing through a capacitor, C1, as shown; and a gate electrode for coupling to an input signal, here an RF input through a capacitor, C2, as shown. It is noted that the source electrode of the transistor Q1 is connected to ground, as shown.

#The circuit 10 includes a bias circuit 12, comprising: a current mirror having: a current source Iref, and biasing circuitry (depletion mode transistors Q2, Q3, and Q4 and diodes Dn) arranged as shown, coupled to the current source Lref, and between the potential more positive than the reference potential (+Vdd) and a potential more negative than the reference potential; coupled to a potential more negative than the reference potential (−Vss). It should be noted that the diodes Dn is a series of a plurality n of diodes GaN diodes Dn, where n is the number of diodes in the series selected in accordance with the voltages used, here for example, Vdd is 24 volts and −Vss is −8.0 volts.