Electric drive power converter with low distortion dead-time insertion

A power conversion method comprising:

• generating PWM upper and lower gate signals for driving a phase leg;
• detecting a current direction from the leg;
• when the direction is positive, driving the leg with delayed rising and advanced falling edges of the lower gate signal and unmodified upper gate signal;
• and
• when the direction is negative, driving the leg with delayed rising and advanced falling edges of the upper gate signal and unmodified lower gate signal.

An electric drive for a transportation vehicle comprising:

• a multi-phase electric traction motor;
• a DC link configured to receive a DC supply voltage;
• a plurality of phase legs coupled between the DC link and the motor, wherein each phase leg comprises:
• a respective upper switching device and a respective lower switching device, wherein a junction between the upper and lower switching devices is coupled to the motor;
• a current sensor for the phase leg detecting a positive or negative direction of a current flow from the junction to the load;
• and
• a gate driver coupled to the phase leg activating the upper switching device according to an upper gate signal and activating the lower switching device according to a lower gate signal;
• and
• a controller comparing a PWM carrier signal to a commanded duty cycle signal to generate respective nominal upper and lower timing signals, wherein when a respective positive direction of current flow is detected then the controller:
• generates a respective positive offset duty cycle which is greater than the commanded duty cycle by a predetermined positive offset;
• compares the PWM carrier signal to the respective positive offset duty cycle signal to generate a respective positive offset timing signal;
• generates the respective upper gate signal according to the respective nominal upper timing signal;
• and
• generates the respective lower gate signal according to the logical inverse of the respective positive offset timing signal;
• and wherein when a respective negative direction of current flow is detected then the controller:
• generates a respective negative offset duty cycle which is less than the commanded duty cycle by a predetermined negative offset;
• compares the PWM carrier signal to the respective negative offset duty cycle signal to generate a respective negative offset timing signal;
• generates the respective upper gate signal according to the respective negative offset timing signal;
• and
• generates the respective lower gate signal according to the respective nominal lower timing signal.