Back to results
US 9,960,671 B2Granted
Isolator with reduced susceptibility to parasitic coupling
AssigneeAvago Technologies General IP (Singapore) Pte. Ltd.
InventorsDominique Ho, Kwee Chong Chang, Kah Weng Lee, Brian J. Misek
Life of this patent
Estimating the term…
Abstract
A capacitive isolation system, capacitive isolator, and method of operating the same are disclosed. The capacitive isolation system is described to include a first semiconductor die and a second semiconductor die each having capacitive elements established thereon and positioned in a face-to-face configuration. An isolation layer is provided between the first and second semiconductor die so as to establish an isolation boundary therebetween. Capacitive coupling is used to carry information across the isolation boundary.
Claims30
An isolator, comprising:
- a first semiconductor die comprising a first surface comprising a plurality of pads established thereon, wherein the plurality of pads established on the first surface of the first semiconductor die include:
- a first capacitive element;
- and
- a first bonding pad that facilitates wirebonding and enables an electrical connection between a first external circuit and the first capacitive element of the first semiconductor die;
- a second semiconductor die comprising a first surface facing the first surface of the first semiconductor die, wherein the first surface of the second semiconductor die comprises a plurality of pads established thereon, wherein the plurality of pads established on the first surface of the second semiconductor die include:
- a second capacitive element, wherein the first semiconductor die and second semiconductor die are positioned relative to one another such that the first capacitive element and second capacitive element oppose one another and at least partially overlap one another to form a capacitor;
- and
- a second bonding pad that facilitates wirebonding and enables an electrical connection between a second external circuit and the second capacitive element of the second semiconductor die;
- and
- an isolation layer positioned between the first surface of the first semiconductor die and the first surface of the second semiconductor die so as to provide an electrical isolation boundary between the first external circuit and the second external circuit, wherein the isolation layer comprises at least one opening that exposes the first bonding pad and/or second bonding pad for wirebonding.
7 more elements
An isolation system, comprising:
- a first lead frame configured for connection to a first external circuit, the first lead frame having a bonding surface and a top surface of a lead that are separated by a first downset distance formed by folding the first lead frame, wherein a first die is mounted on the bonding surface of the first lead frame;
- a second lead frame configured for connection to a second external circuit, the second lead frame having a bonding surface and a top surface of a lead that are separated by a second downset distance formed by folding the second lead frame, wherein a second die is mounted on the bonding surface of the second lead frame, wherein the first die and second die each have one or more capacitive elements established thereon, wherein the bonding surface of the first lead frame and the bonding surface of the second lead frame at least partially overlap and face one another, and wherein the first die and second die are positioned in a face-to-face configuration thereby creating one or more isolation capacitors between the first die and second die with overlapping capacitive elements;
- and
- an isolation layer positioned between the first die and the second die so as to create an electrical isolation boundary between the first external circuit and the second external circuit.
1 more element
A capacitive isolator, comprising:
- a first lead frame;
- a second lead frame;
- a first semiconductor die mounted to the first lead frame and having a first transmitting capacitive element;
- a second semiconductor die mounted to the second lead frame and having a first receiving capacitive element, the second semiconductor die and first semiconductor die being positioned in a face-to-face configuration so as to at least partially overlap the first transmitting capacitive element with the first receiving capacitive element and create one or more isolation capacitors between the first the first semiconductor die and the second semiconductor die, wherein the first lead frame and the second lead frame are also mounted in a face-to-face configuration so as to at least partially overlap one another, and wherein the first lead frame and the second lead frame are both folded so as to at least partially surround sides of the first semiconductor die and second semiconductor die, thereby establishing a Faraday shield around the first semiconductor die and second semiconductor die;
- and
- an isolation layer provided between the first semiconductor die and the second semiconductor die to create an electrical isolation boundary between the first transmitting capacitive element and the first receiving capacitive element.
3 more elements
A capacitive isolation system, comprising:
- a first lead frame;
- a first die mounted on the first lead frame and having a first capacitive element formed thereon or therein;
- a second lead frame;
- a second die mounted on the second lead frame and having a second capacitive element formed thereon or therein, wherein the first and second capacitive elements are positioned in proximity to one another and are also positioned in an at least a partial overlapping relationship to establish an isolation capacitor therebetween, and wherein the first lead frame and second lead frame are also positioned in at least a partial overlapping relationship and are folded so as to create a Faraday shield around three dimensions of the isolation capacitor;
- and
- an isolation layer residing between the first capacitive element and the second capacitive element.
3 more elements
Dependencies are inferred from the claim text.