US 9,960,596 B2Granted

Automatic voltage switching circuit for selecting a higher voltage of multiple supply voltages to provide as an output voltage

AssigneeQUALCOMM Incorporated

InventorsBurt Lee Price, Yeshwant Nagaraj Kolla, Neel Shashank Natekar

Life of this patent

Estimating the term…

Loading patent…

Abstract

Automatic voltage switching circuits for providing a higher voltage of multiple supply voltages are disclosed. In one aspect, an automatic voltage switching circuit is configured to generate a compare signal indicating which of a first supply voltage and a second supply voltage is a higher voltage. The automatic voltage switching circuit is further configured to generate first and second select signals based on the compare signal, wherein the first and second select signals are in a voltage domain of the higher voltage. Transistors corresponding to the first and second supply voltages control switching the output voltage to the higher voltage in response to the first and second select signals. Biasing the back-gates of the transistors using the output voltage reduces or avoids forward biasing in the body diodes of the transistors, thus reducing the possibility of the output voltage causing interference on a power supply corresponding to a non-activated transistor.

Claims24

Dependent claims

An automatic voltage switching circuit, comprising:

a voltage comparator circuit configured to generate a compare signal indicating which of a first supply voltage and a second supply voltage is a higher voltage;
a voltage output circuit, comprising:
a voltage level shifter circuit configured to generate:
a first select signal based on the compare signal indicating the first supply voltage is the higher voltage of the first supply voltage and the second supply voltage, wherein the first select signal is in a voltage domain of the higher voltage;
and
a second select signal based on the compare signal indicating the second supply voltage is the higher voltage of the first supply voltage and the second supply voltage, wherein the second select signal is in the voltage domain of the higher voltage;
and
a back-gate biased selector circuit, comprising:
a first transistor, comprising a first node configured to receive the first supply voltage, a gate configured to receive the first select signal, a second node configured to provide an output voltage from the first node of the first transistor in response to the gate of the first transistor being activated by the first select signal, and a back-gate configured to receive the output voltage;
and
a second transistor, comprising a first node configured to receive the second supply voltage, a gate configured to receive the second select signal, a second node configured to provide the output voltage from the first node of the second transistor in response to the gate of the second transistor being activated by the second select signal, and a back-gate configured to receive the output voltage;
a first default transistor, comprising:
a gate configured to receive the second supply voltage;
a first node configured to receive the first supply voltage;
and
a second node electrically coupled to the gate of the second transistor of the back-gate biased selector circuit and configured to provide the first supply voltage from the first node of the first default transistor in response to the gate of the first default transistor being activated in response to the second supply voltage being unavailable, wherein the gate of the second transistor of the back-gate biased selector circuit deactivates in response to the first supply voltage;
and
a second default transistor, comprising:
a gate configured to receive the second supply voltage;
a first node electrically coupled to a ground voltage source;
and
a second node electrically coupled to the gate of the first transistor of the back-gate biased selector circuit and configured to provide a ground voltage from the first node of the second default transistor in response to the gate of the second default transistor being activated in response to the second supply voltage being unavailable, wherein the gate of the first transistor of the back-gate biased selector circuit activates in response to the ground voltage.

19 more elements

A power switch system, comprising:

a power switch circuit, comprising:
a first transistor, comprising a gate configured to receive a first enable signal shifted into a voltage domain of an output voltage, a source configured to receive a first supply voltage, and a drain coupled to a powered circuit;
and
a second transistor, comprising a gate configured to receive a second enable signal shifted into the voltage domain of the output voltage, a source configured to receive a second supply voltage, and a drain coupled to the powered circuit;
and
an automatic voltage switching circuit, comprising:
a voltage comparator circuit configured to generate a compare signal indicating which of the first supply voltage and the second supply voltage is a higher voltage;
a voltage level shifter circuit configured to generate:
a first select signal based on the compare signal indicating the first supply voltage is the higher voltage of the first supply voltage and the second supply voltage, wherein the first select signal is in a voltage domain of the higher voltage;
and
a second select signal based on the compare signal indicating the second supply voltage is the higher voltage of the first supply voltage and the second supply voltage, wherein the second select signal is in the voltage domain of the higher voltage;
and
a back-gate biased selector circuit, comprising:
a first transistor, comprising a first node configured to receive the first supply voltage, a gate configured to receive the first select signal, a second node configured to provide the output voltage from the first node of the first transistor in response to the gate of the first transistor being activated by the first select signal, and a back-gate configured to receive the output voltage;
and
a second transistor, comprising a first node configured to receive the second supply voltage, a gate configured to receive the second select signal, a second node configured to provide the output voltage from the first node of the second transistor in response to the gate of the second transistor being activated by the second select signal, and a back-gate configured to receive the output voltage;
a first default transistor, comprising:
a gate configured to receive the second supply voltage;
a first node configured to receive the first supply voltage;
and
a second node electrically coupled to the gate of the second transistor of the back-gate biased selector circuit and configured to provide the first supply voltage from the first node of the first default transistor in response to the gate of the first default transistor being activated in response to the second supply voltage being unavailable, wherein the gate of the second transistor of the back-gate biased selector circuit deactivates in response to the first supply voltage;
and
a second default transistor, comprising:
a gate configured to receive the second supply voltage;
a first node electrically coupled to a ground voltage source;
and
a second node electrically coupled to the gate of the first transistor of the back-gate biased selector circuit and configured to provide a ground voltage from the first node of the second default transistor in response to the gate of the second default transistor being activated in response to the second supply voltage being unavailable, wherein the gate of the first transistor of the back-gate biased selector circuit activates in response to the ground voltage.

24 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/862,773Filed 23 Sep 2015 · us provisional application
Priority: 15 Apr 2015
Published: US 2016/0308355 A120 Oct 2016
Granted: 1 May 2018
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

H02J 1/10
Circuit arrangements for DC mains or DC distribution networks: parallel operation of DC sources
H03K 5/2481
Using field effect transistors: with at least one differential stage
H03K 19/00315
Modifications for increasing the reliability for protection: in field-effect transistor circuits
H03K 19/0016
Arrangements for reducing power consumption: by using a control or a clock signal, e.g. in order to apply power supply