Metal oxide thin film transistor with source and drain regions doped at room temperature

#This disclosure relates generally to thin film transistors that include a metal oxide active layer with source and drain regions having a reduced resistivity relative to the metal oxide based on doping of the source and drain regions at room temperature.

#A thin-film transistor (TFT) consists of a channel region located between source and drain (S/D) regions. The resistance of the channel is modulated by the voltage on the gate electrode, while that of the S/D regions is not. For a conventional metal-oxide (MO)TFT, metal is used to contact the S/D regions, forming Schottky barriers at the junction where the metal contacts the metal oxide in the S/D regions. The resistance associated with such a junction is high, resulting in lowering of the on-state current. Accordingly mechanisms to reduce the resistance of the S/D regions are desired.

#In some aspects, high resistance associated with the Schottky barrier can be reduced if the resistivity of the metal oxide region under the metal coverage is decreased. Existing techniques for decreasing the resistivity of the S/D regions incorporate extrinsic dopants into the metal oxide of the S/D, conventionally including two steps. The dopants are first injected into the S/D regions and then activated by the heat-treatments to supply carriers. However, the activation annealing step not only reduces the S/D resistivity but also potentially generates defects in the channel and drives dopants to diffuse into the channel, shortening the effective channel length and possibly degrading the transistor characteristics.

#Non-limiting and non-exhaustive embodiments of the subject disclosure are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

#FIG. 1 presents a cross-sectional view of a bottom gate TFT that includes a metal oxide active layer with S/D regions having a reduced resistivity relative to the metal oxide based on doping of the S/D regions without thermal annealing, in accordance with aspects and embodiments described herein;

#FIG. 2 presents a cross-sectional view of a top gate TFT that includes a metal oxide active layer with S/D regions having a reduced resistivity relative to the metal oxide based on doping of the S/D regions without thermal annealing, in accordance with aspects and embodiments described herein;

#Various aspects or features of this disclosure are described with reference to the drawings, wherein like reference numerals are used to refer to like elements throughout. In this specification, numerous specific details are set forth in order to provide a thorough understanding of the subject disclosure. It should be understood, however, that the certain aspects of this disclosure may be practiced without these specific details, or with other methods, components, materials, etc. In other instances, well-known structures and devices are shown in block diagram form to facilitate describing the subject disclosure.

#By way of introduction, the subject matter disclosed herein relates to techniques to effectively dope the S/D regions of a MOTFT without the need of activation annealing by fabricating the MOTFT with room-temperature doped S/D regions. As a result, the activation induced defect wherein dopants laterally diffuse from the S/D regions into the channel region is avoided, enhancing the transistor performance. For example, without the lateral diffusion of dopants from S/D regions into channel caused by activation annealing, the overlap region between the gate electrode and the S/D can be minimized, notably reducing the parasitic capacitance and thus offering a higher device switching speed. In addition, the channel length can be shorted because the extra channel length included in conventional MOTFTs to compensate for the dopant diffusion is not needed, allowing for the fabrication of MOTFTs with ultra-short channels (e.g., approximately less than 100 nm) and improving the scalability of the MOTFT. The elimination of the heat-treatment step also lowers transistor manufacturing cost. Further, the subject room-temperature doping technique significantly lowers the process temperature for the MOTFT with S/D regions having a reduced resistivity based on doping. As a result the subject MOTFT can be formed using a heat sensitive substrate that cannot otherwise withstand the high temperatures associated with post ion implantation annealing, including a flexible substrate formed with polymer, thus enabling its application on flexible displays.

#In an aspect a transistor structure is provided, that includes a substrate, and source and drain regions within a doped active layer having resulted from doping of an active layer comprising metal-oxide and formed on the substrate, wherein the doped active layer was doped without thermal annealing (e.g., a temperature between about 20° C. and 26° C.), thereby resulting in a reduction of a resistivity of the source and drain regions of the doped active layer relative to the active layer prior to the doping. In an aspect, the source and drain regions have a resistivity of about 10 mΩ·cm after being doped a high concentration of stable ions and without subsequent activation of the ions via annealing. For example, when the metal oxide layer is formed with zinc oxide (ZnO), the implantation of both phosphorus and silicon into ZnO at room temperature and without thermal annealing at a concentration of about 1021cm−3 can effectively reduce the ρ of ZnO to near or below 10 mΩ·cm.