Integrated circuit structure with substrate isolation and un-doped channel

A semiconductor structure, comprising:

• a first and a second fin features formed on a substrate;
• a field effect transistor (FET) formed on the first fin feature, wherein the FET includes a gate stack formed over the first fin feature;
• source/drain features over the substrate and disposed on opposing sides of the gate stack;
• a channel region defined in the first fin feature and underlying the gate stack;
• and a buried isolation feature disposed vertically between the channel region and the substrate, wherein the buried isolation feature includes an oxide of a compound semiconductor;
• and
• a semiconductor device formed on the second fin feature, wherein the semiconductor device is selected from the group consisting of a diode, a contact pickup, a bipolar junction transistor, and a combination thereof, wherein the second fin feature is disposed on a semiconductor feature of the compound semiconductor material.

A semiconductor structure, comprising:

• a first and a second fin features formed on a substrate;
• a field effect transistor (FET) formed on the first fin feature, wherein the FET includes a gate stack formed over the first fin feature;
• source/drain features over the substrate and disposed on opposing sides of the gate stack;
• a channel region defined in the first fin feature and underlying the gate stack;
• and a buried isolation feature disposed vertically between the channel region and the substrate, wherein the buried isolation feature includes an oxide of a compound semiconductor, wherein sidewalls of the buried isolation feature are in contact with and covered by a shallow trench isolation (STI) feature;
• and
• a semiconductor device formed on the second fin feature, wherein the semiconductor device is selected from the group consisting of a diode, a contact pickup, a bipolar junction transistor, and a combination thereof, wherein the second fin feature is disposed on a semiconductor feature of the compound semiconductor material, wherein sidewalls of the semiconductor feature are covered by a semiconductor oxide layer.