Bottom contact resistance reduction on VFET
AssigneeInternational Business Machines Corporation
InventorsRuqiang Bao, ChoongHyun Lee, Shogo Mochizuki, Hemanth Jagannathan
Life of this patent
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Abstract
Embodiments are directed to a method and resulting structures for a vertical field effect transistor (VFET) having a reduced bottom contact resistance. A multilayered bottom doped region having alternating doped layers and doped sacrificial layers is formed on a substrate. One or more cavities are formed by removing portions of the doped sacrificial layers. A bottom contact is formed over the multilayered bottom doped region. The bottom contact includes one or more conductive flanges that fill the cavities.
Claims18
A method for forming a semiconductor device, the method comprising:
- forming a multilayered bottom doped region comprising alternating doped layers and doped sacrificial layers on a substrate;
- forming one or more cavities by removing portions of the doped sacrificial layers;
- and
- forming a bottom contact over the multilayered bottom doped region, said bottom contact comprising one or more conductive flanges filling the cavities.
A method for forming a semiconductor device, the method comprising:
- forming a semiconductor fin on a substrate;
- forming a multilayered bottom doped region comprising alternating doped layers and doped sacrificial layers on the substrate and adjacent to sidewalls of the semiconductor fin;
- forming a conductive gate over a channel region of the semiconductor fin;
- forming a bottom spacer between the conductive gate and the multilayered bottom doped region;
- doping a portion of the semiconductor fin between the bottom spacer and the substrate;
- forming one or more cavities by removing portions of the doped sacrificial layers;
- and
- forming a bottom contact over the multilayered bottom doped region, said bottom contact comprising one or more conductive flanges filling the cavities;
- wherein the one or more conductive flanges extend from the bottom contact to the doped portion of the semiconductor fin.
A method for forming a semiconductor device, the method comprising:
- forming a semiconductor fin on a substrate;
- forming a multilayered bottom doped region comprising alternating doped layers and doped sacrificial layers on the substrate and adjacent to sidewalls of the semiconductor fin;
- forming a conductive gate over a channel region of the semiconductor fin;
- forming a bottom spacer between the conductive gate and the multilayered bottom doped region;
- doping a portion of the semiconductor fin between the bottom spacer and the substrate;
- forming one or more cavities by removing portions of the doped sacrificial layers;
- and
- forming a bottom contact over the multilayered bottom doped region, said bottom contact comprising one or more conductive flanges filling the cavities;
- wherein a portion of the doped sacrificial layers remains between the one or more conductive flanges and the doped portion of the semiconductor fin.
Dependencies are inferred from the claim text.