Method of forming vertical field effect transistors with different threshold voltages and the resulting integrated circuit structure

A method comprising:

• providing a semiconductor layer;
• forming a stack of sacrificial layers on the semiconductor layer, the forming of the stack comprising:
• forming a first sacrificial layer on a first device region of the semiconductor layer;
• forming a second sacrificial layer on a second device region of the semiconductor layer and on the first sacrificial layer;
• forming a third sacrificial layer over the second sacrificial layer;
• and
• forming a fourth sacrificial layer over the third sacrificial layer such that the stack of sacrificial layers has a first portion on the first device region and a second portion on the second device region and such that, within the first portion, the first sacrificial layer is an extra sacrificial layer;
• etching a first multi-layer fin in the first portion and the semiconductor layer and a second multi-layer fin in the second portion and the semiconductor layer;
• and
• concurrently forming a first vertical field effect transistor using the first multi-layer fin and a second vertical field effect transistor using the second multi-layer fin, the concurrently forming comprising:
• forming a first upper dielectric spacer above a first gate and on first sidewalls of the first multi-layer fin and a second upper dielectric spacer above a second gate and on second sidewalls of the second multi-layer fin;
• and
• performing multiple etch processes that remove the sacrificial layers from the first multi-layer fin and the second multi-layer fin to create a first semiconductor fin and a second semiconductor fin, respectively,
• wherein the multiple etch processes comprise:
• initial etch processes that remove all of the sacrificial layers except the extra sacrificial layer on the first multi-layer fin;
• and
• an isotropic etch process that removes the extra sacrificial layer from the first multi-layer fin and etches back the first upper dielectric spacer and the second upper dielectric spacer,
• wherein, during the isotropic etch process, the first upper dielectric spacer is partially protected by the extra sacrificial layer until the extra sacrificial layer is removed such that the second upper dielectric spacer is etched back faster than the first upper dielectric spacer and such that, following the isotropic etch process, the first upper dielectric spacer is positioned laterally adjacent to the first semiconductor fin, the second upper dielectric spacer is positioned laterally adjacent to the second semiconductor fin, and the first upper dielectric spacer is taller than the second upper dielectric spacer.