Field effect transistor and method of manufacturing the same
AssigneeMitsubishi Electric Corporation
InventorTakahiro Nakamoto
Life of this patent
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Abstract
A field effect transistor according to the present invention includes a semiconductor layer including a groove, an insulating film formed on an upper surface of the semiconductor layer and having an opening above the groove and a gate electrode buried in the opening to be in contact with side surfaces and a bottom surface of the groove and having parts being in contact with an upper surface of the insulating film on both sides of the opening, wherein the gate electrode has a T-shaped sectional shape in which a width of an upper end is larger than a width of the upper surface of the insulating film.
Claims11
A field effect transistor comprising:
- a semiconductor layer including a groove;
- an insulating film formed on an upper surface of the semiconductor layer and having an opening above the groove;
- and
- a gate electrode buried in the opening to be in contact with side surfaces and a bottom surface of the groove, the gate having a T-shaped sectional shape and including an upper end and a lower end, the lower end being in contact with an upper surface of the insulating film on both sides of the opening,
- wherein a width of the upper end is larger than a width of the lower end.
A method of manufacturing a field effect transistor, comprising:
- a step of forming an insulating film on an upper surface of a semiconductor layer;
- a step of forming an opening in the insulating film;
- and
- a step of forming a gate electrode to bury the opening, the gate electrode having a T-shaped sectional shape and including an upper end and a lower end, the lower end being in contact with an upper surface of the insulating film on both sides of the opening,
- wherein the step of forming the gate electrode includes
- a step of forming at the lower end a lower electrode made of Pt to be in contact with the semiconductor layer in the opening, and
- a step of executing thermal treatment to the gate electrode to sink the lower electrode in the semiconductor layer,
- wherein a width of an upper end is larger than a width of the lower end.
Dependencies are inferred from the claim text.