US 9,960,256 B2Granted

Merged gate and source/drain contacts in a semiconductor device

AssigneeGlobalfoundries Inc.

InventorsGuillaume Bouche, Andy Chih-Hung Wei

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Abstract

Provided are approaches for forming merged gate and source/drain (S/D) contacts in a semiconductor device. Specifically, one approach provides a dielectric layer over a set of gate structures formed over a substrate; a set of source/drain (S/D) openings patterned in the dielectric layer between the gate structures; a fill material formed over the gate structures, including within the S/D openings; and a set of gate openings patterned over the gate structures, wherein a portion of the dielectric layer directly adjacent the fill material formed within one of the S/D openings is removed. The fill material is then removed, selective to the dielectric layer, and a metal material is deposited over the semiconductor device to form a set of gate contacts within the gate openings, and a set of S/D contacts within the S/D openings, wherein one of the gate contacts and one of the S/D contacts are merged.

Claims11

Dependent claims

A method of forming a semiconductor device, the method comprising:

forming a set of contact placeholders over both a set of fins and a capping layer over the set of fins, the set of contact placeholders comprising nitride atop an oxide;
providing a dielectric layer over a set of gate structures formed over a substrate and over the set of contact placeholders;
patterning a set of source/drain (S/D) openings in the dielectric layer between the set of gate structures;
removing the nitride from atop the oxide;
removing the oxide selective to the dielectric layer and the capping layer;
and
forming a fill material over the set of gate structures, including within the set of S/D openings;
patterning a set of gate openings over the set of gate structures, wherein a portion of the dielectric layer directly adjacent the fill material formed within one of the set of S/D openings is removed, and at least one gate opening of the set of gate openings exposes on a bottom of the gate opening only a part or all of one gate structure of the set of gate structures;
removing the fill material selective to the dielectric layer;
and
removing the capping layer from atop the set of gate structures within the set of gate openings and from atop the set of fins within the set of S/D openings.

8 more elements

A method for forming merged gate and source/drain (S/D) contacts in a semiconductor device, the method comprising:

forming a set of contact placeholders over both a set of fins and a capping layer over the set of fins, the set of contact placeholders comprising nitride atop an oxide;
providing a dielectric layer over a set of gate structures formed over a substrate and over the set of contact placeholders;
patterning a set of source/drain (S/D) openings in the dielectric layer between the set of gate structures;
removing the nitride from atop the oxide;
removing the oxide selective to the dielectric layer and the capping layer;
forming a deep ultraviolet light absorbing oxide (DUO) fill over the set of gate structures, including within the set of S/D openings;
patterning a set of gate openings over the set of gate structures, wherein a portion of the dielectric layer directly adjacent the DUO fill formed within one of the set of S/D openings is removed, and at least one gate opening of the set of gate openings exposes on a bottom of the gate opening only a part or all of one gate structure of the set of gate structures;
removing the DUO fill selective to the dielectric layer;
and
removing the capping layer from atop the set of gate structures within the set of gate openings and from atop a set of fins within the set of STD openings.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/282,089Filed 20 May 2014
Published: US 2015/0340467 A126 Nov 2015
Granted: 1 May 2018
Term ends: Not estimatedThe source records don’t support an estimate.

Classification12 codes

H10D 30/024
Of FETs having insulated gates [IGFET]: of fin field-effect transistors [FinFET]
H10D 30/62
Insulated-gate field-effect transistors [IGFET]: fin field-effect transistors [FinFET]
H10D 30/6219
Fin field-effect transistors [FinFET]: characterised by the source or drain electrodes
H10D 48/30
Individual devices not covered by groups H10D1/00 - H10D44/00: devices controlled by electric currents or voltages