Horizontal nanosheet FETs and methods of manufacturing the same

#Horizontal nanosheet (hNS) field effect transistors (FETs) having InGaAs channels offer the possibility of high mobility, high injection velocity, and low gate capacitance. However, InGaAs hNS FETs also tend to have small bandgaps, such as approximately 750 meV or even less than 1.1 eV for silicon. A consequence of this small direct bandgap is a large amount of band-to-band tunneling (BTBT) leakage current, which is further exacerbated by the parasitic bipolar effect (PBE) that is present in all gate-all-around (GAA) FETs. Parasitic leakage, which is a combination of the BTBT leakage and PBE gain, is exponentially sensitive to positive supply voltage (VDD) and channel length. BTBT occurs in regions of strong band-bending, which exists in the transition region between the channel and the high-doped portion of the drain extension. In related art hNS FETs in which the effective channel length (Leff) is approximately equal to the gate length (LG), the hNS FETs have very high BTBT leakage and are unusable for a mobile system on a chip (SOC) operating at supply voltages of 0.75V or higher. Additionally, the channel length sensitivity presents a significant scaling limitation because hNS FETs with an Leff of approximately 15 nm may not be able to operate with VDD above approximately 0.7V without incurring excessive BTBT leakage.

#In the related art, this significant scaling limitation may be addressed by configuring the FET such that the Leff is longer than the LG. Increasing Leff by shifting the PN junction away from the gate edges reduces band curvature and exponentially reduces BTBT leakage. Increasing the Leff also reduced PBE gain, which has a near-exponential sensitivity to channel length. The Leff could be increased, for instance, up to two spacer thicknesses larger than the LG. However, in related art hNS FETs, increasing Leff reduces the electron concentration in the extension regions and thus increases parasitic resistance (Rpara). The resulting increase in Rpara may render the hNS FET unsuitable. Accordingly, in related art hNS FETs, there is a tradeoff between BTBT leakage and Rpara (e.g., the BTBT leakage of related art hNS FETs may be reduced by increasing the Leff, but this reduction in BTBT leakage is at the expense of increasing the Rpara of the hNS FET).

#The present disclosure is directed to various embodiments of a horizontal nanosheet (hNS) field effect transistor (FET). In one embodiment, the hNS FET includes a source electrode, a drain electrode, a gate electrode between the source electrode and the drain electrode, a first spacer separating the source electrode from the gate electrode, a second spacer separating the drain electrode from the gate electrode, a channel region under the gate electrode extending between the source electrode and the drain electrode, and at least one layer of crystalline barrier material. The source electrode and the drain electrode each include an extension region. The extension region of the source electrode is under at least a portion of the first spacer and the extension region of the drain electrode is under at least a portion of the second spacer. The layer of crystalline barrier material has a first thickness at the extension regions of the source and drain electrodes and a second thickness less than the first thickness at the channel region. The first thickness of the layer of crystalline barrier material at the extension regions of the source and drain electrodes may be from approximately 3 nm to approximately 5 nm and the second thickness of the layer of crystalline barrier material at the channel region may be from approximately 1 nm to approximately 2 nm. The first thickness of the layer of crystalline barrier material at the extension regions of the source and drain electrodes may be from approximately 0.5 nm to approximately 5 nm and the second thickness of the layer of crystalline barrier material at the channel region may be substantially zero. The at least one layer may include a first layer of crystalline barrier material above the extension regions of the source and drain electrodes and a second layer of crystalline barrier material below the extension regions of the source and drain electrodes. The crystalline barrier material may be InP, InGaP, InAlA, AlAsSb, or combinations thereof.

#These and other features and advantages of embodiments of the present disclosure will become more apparent by reference to the following detailed description when considered in conjunction with the following drawings. In the drawings, like reference numerals are used throughout the figures to reference like features and components. The figures are not necessarily drawn to scale.

#FIG. 1 is a schematic cross-sectional view of a horizontal nanosheet (hNS) field effect transistor (FET) according to one embodiment of the present disclosure;

#FIG. 2 is a graph comparing the carrier mobility of a hNS FET having one or more layers of crystalline barrier material according to one embodiment of the present disclosure to the carrier mobility of a conventional hNS FET; and

#The present disclosure is directed to various embodiments of a horizontal nanosheet (hNS) field effect transistor (FET) and various methods of manufacturing the horizontal nanosheet field effect transistor. The horizontal nanosheet field effect transistor according to one embodiment of the present disclosure includes one or more layers of crystalline barrier material (CBM) at the drain electrode extension region and/or at the source electrode extension region. Additionally, according to one or more embodiments of the present disclosure, the one or more layers of CBM either do not extend to a channel region of the hNS FET or the one or more layers of CBM are thinner at the channel region compared to the source and drain extension regions. The one or more layers of CBM are configured to increase electron mobility in the extension regions of the source and drain electrodes by suppressing surface roughness scattering (SRS), which would otherwise occur at the interface between the crystalline channel and a non-crystalline overlayer. Reducing the thickness of the one or more layers of CBM at the channel region compared to the extension regions, or not providing the one or more layers of CBM in the channel region, is configured to increase electron mobility in the extension regions without increasing the equivalent oxide thickness (EOT) of the hNS FET, which would be detrimental to the short channel effects (SCE) performance of the hNS FET and would not be a practical solution for the 5 nm node and beyond. Additionally, according to one or more embodiments, the extension regions of the source and drain electrodes are lightly doped and the effective length of the channel is greater than the length of the gate. Reducing the doping in the extension regions and increasing the effective length of the channel is configured to reduce the parasitic leakage of the hNS FET. Together, the effective length of the channel, the light doping of the extension regions, and the one or more layers of CBM in the extension regions are configured to reduce the parasitic leakage of the hNS FET while not increasing or substantially not increasing the parasitic resistance of the hNS FET. Accordingly, unlike related art hNS FETs, in the hNS FET of the present disclosure there is not a tradeoff between parasitic leakage and parasitic resistance.

#Hereinafter, example embodiments will be described in more detail with reference to the accompanying drawings, in which like reference numbers refer to like elements throughout. The present invention, however, may be embodied in various different forms, and should not be construed as being limited to only the illustrated embodiments herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey the aspects and features of the present invention to those skilled in the art. Accordingly, processes, elements, and techniques that are not necessary to those having ordinary skill in the art for a complete understanding of the aspects and features of the present invention may not be described. Unless otherwise noted, like reference numerals denote like elements throughout the attached drawings and the written description, and thus, descriptions thereof may not be repeated.

#In the drawings, the relative sizes of elements, layers, and regions may be exaggerated and/or simplified for clarity. Spatially relative terms, such as “beneath,” “below,” “lower,” “under,” “above,” “upper,” and the like, may be used herein for ease of explanation to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or in operation, in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” or “under” other elements or features would then be oriented “above” the other elements or features. Thus, the example terms “below” and “under” can encompass both an orientation of above and below. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.