Standard cell architecture for parasitic resistance reduction
AssigneeQUALCOMM Incorporated
InventorsXiangdong Chen, Hyeokjin Bruce Lim, Satyanarayana Sahu, Venugopal Boynapalli
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AssigneeQUALCOMM Incorporated
InventorsXiangdong Chen, Hyeokjin Bruce Lim, Satyanarayana Sahu, Venugopal Boynapalli
Estimating the term…
A MOS IC may include a first contact interconnect in a first standard cell that extends in a first direction and contacts a first MOS transistor source and a voltage source. Still further, the MOS IC may include a first double diffusion break extending along a first boundary in the first direction of the first standard cell and a second standard cell. The MOS IC may also include a second contact interconnect extending over a portion of the first double diffusion break. In an aspect, the second contact interconnect may be within both the first standard cell and the second standard cell and coupled to the voltage source. Additionally, the MOS IC may include a third contact interconnect extending in a second direction orthogonal to the first direction and couples the first contact interconnect and the second contact interconnect together.
A metal oxide semiconductor (MOS) integrated circuit (IC) including a first standard cell and a second standard cell adjacent the first standard cell, the MOS IC comprising:
A method of operation of a metal oxide semiconductor (MOS) integrated circuit (IC) including a first standard cell and a second standard cell adjacent the first standard cell, the method comprising:
A metal oxide semiconductor (MOS) integrated circuit (IC) including a first standard cell and a second standard cell adjacent the first standard cell, the MOS IC comprising:
Dependencies are inferred from the claim text.