Molded image sensor chip scale packages and related methods
AssigneeSemiconductor Components Industries, LLC
InventorWeng-Jin Wu
Life of this patent
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Abstract
Implementations of a molded image sensor chip scale package may include an image sensor having a first side and a second side. A first cavity wall and a second cavity wall may be coupled to the first side of the image sensor and extend therefrom. The first cavity wall and the second cavity wall may form a cavity over the image sensor. A transparent layer may be coupled to the first cavity wall and the second cavity wall. A redistribution layer (RDL) may be coupled to the second side of the image sensor. At least one interconnect may be directly coupled to the RDL. A mold material may encapsulate a portion of the RDL, a portion of the image sensor, and a side of each cavity wall, and a portion of the transparent layer.
Claims19
A chip scale package comprising:
- an image sensor comprising a first side and a second side;
- a first cavity wall and a second cavity wall coupled to the first side of the image sensor and extending therefrom, wherein the first cavity wall and the second cavity wall form a cavity over the image sensor;
- a transparent layer coupled to the first cavity wall and to the second cavity wall;
- a redistribution layer (RDL) coupled to the second side of the image sensor;
- at least one interconnect directly coupled to the RDL;
- and
- a mold material, wherein the mold material encapsulates a portion of the RDL, a portion of the image sensor, a side of each cavity wall, and a portion of the transparent layer;
- and
- wherein the mold material directly covers a first interface between the transparent layer and the first cavity wall and a second interface between the transparent layer and the second cavity wall.
A method of forming a chip scale package comprising:
- providing a wafer comprising a first side and a second side, the wafer comprising a plurality of image sensors;
- coupling the first side of the wafer to a first side of a plurality of cavity walls;
- coupling a transparent layer to a second side of the plurality of cavity walls;
- coupling a redistribution layer (RDL) to the second side of the wafer;
- forming an interconnect array on the RDL;
- forming a plurality of notches between each image sensor, wherein the plurality of notches extends from the image sensor into the transparent layer;
- placing a mold material over the interconnect array to encapsulate a portion of the RDL;
- filling the plurality of notches with the mold material, wherein the mold material directly covers a plurality of interfaces between the transparent layer and the plurality of cavity walls;
- and
- singulating each image sensor at each notch of the plurality of notches to form a plurality of chip scale packages.
A method of forming a chip scale package comprising:
- providing a wafer comprising a first side and a second side, the wafer comprising a plurality of image sensors;
- coupling the first side of a wafer to a first side of a plurality of cavity walls;
- coupling a transparent layer to a second side of the plurality of cavity walls;
- coupling a redistribution layer (RDL) to the second side of the wafer;
- forming an interconnect array on the RDL;
- forming a plurality of notches between each image sensor, wherein the plurality of notches extends from the image sensor into the transparent layer;
- placing a mold material over the interconnect array;
- laminating the mold material to press the interconnect array through the mold material to encapsulate a portion of the RDL;
- laminating the mold material into each notch of the plurality of notches, wherein the mold material directly covers a plurality of interfaces between the transparent layer and the plurality of cavity walls;
- and
- singulating each image sensor at each notch of the plurality of notches to form a plurality of chip scale packages.
Dependencies are inferred from the claim text.