FDSOI-capacitor

A semiconductor device, comprising

• a wafer comprising a semiconductor substrate and having a first region, a second region, and a third region;
• an insulating layer positioned above said semiconductor substrate in said first region and above said semiconductor substrate in a first portion of said second region but not above a second portion of said second region;
• a capacitor structure positioned in at least said first region and comprising a first capacitor electrode, a capacitor insulator, and a second capacitor electrode, wherein said first capacitor electrode comprises a doped region of said semiconductor substrate that is positioned below at least said insulating layer in said first region, wherein said capacitor insulator comprises said insulating layer in said first region and a high-k dielectric layer positioned above said insulating layer, and wherein said second capacitor electrode comprises a conductive layer positioned above said capacitor insulator;
• and
• a transistor device positioned in at least one of said first portion of said second region and said third region of said wafer.

A semiconductor device, comprising:

• a semiconductor-on-insulator (SOI) wafer comprising a semiconductor substrate, a buried insulating layer positioned above said semiconductor substrate, and a semiconductor layer positioned above said buried insulating layer;
• a trench isolation structure positioned in said SOI wafer, said trench isolation structure defining a first region of said SOI wafer and a second region of said SOI wafer, wherein said semiconductor layer is not present above said buried insulating layer in said first region, and wherein said buried insulating layer and said semiconductor layer are not present in a first portion of said second region adjacent to said trench isolation structure;
• a high-k dielectric layer positioned above said buried insulating layer in said first region;
• a conductive layer positioned above said high-k dielectric layer in said first region;
• a doped region positioned in said semiconductor substrate, wherein a first part of said doped region is positioned below said buried insulating layer and said high-k dielectric layer in said first region, and wherein a second part of said doped region is positioned in said at least said first portion of said second region;
• a first contact element conductively coupled to said conductive layer in said first region;
• and
• a second contact element conductively coupled to said second part of said doped region in said first portion of said second region.