US 9,960,179 B2Granted

Semiconductor memory device and method for manufacturing same

AssigneeToshiba Memory Corporation

InventorKenta Yamada

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Abstract

A semiconductor memory device includes a conductive layer; electrode layers stacked on the conductive layer; an insulating body extending through the electrode layers; and a semiconductor layer positioned between the insulating body and the electrode layers. The plurality of electrode layers include a first electrode layer, a second electrode layer provided between the conductive layer and the first electrode layer, and a third electrode layer provided between the conductive layer and the second electrode layer, and the semiconductor layer has a first layer thickness between the insulating body and the first electrode layer, a second layer thickness between the insulating body and the second electrode layer and a third layer thickness between the insulating body and the third electrode layer. The first layer thickness is thinner than the second layer thickness, and the second layer thickness is thinner than the third layer thickness.

Claims15

Dependent claims

A semiconductor memory device comprising:

a conductive layer;
a plurality of electrode layers stacked on the conductive layer;
an insulating body extending through the plurality of electrode layers;
and
a semiconductor layer positioned between the insulating body and the plurality of electrode layers, the semiconductor layer extending along the insulating body, the plurality of electrode layers including a first electrode layer, a second electrode layer provided between the conductive layer and the first electrode layer, and a third electrode layer provided between the conductive layer and the second electrode layer, and
the semiconductor layer having a first layer thickness in a direction from the insulating body to the first electrode layer between the insulating body and the first electrode layer, a second layer thickness in a direction from the insulating body to the second electrode layer between the insulating body and the second electrode layer and a third layer thickness in a direction from the insulating body to the third electrode layer between the insulating body and the third electrode layer,
the first layer thickness being thinner than the second layer thickness, and
the second layer thickness being thinner than the third layer thickness.

5 more elements

A semiconductor memory device comprising:

a conductive layer;
a plurality of electrode layers stacked on a front surface of the conductive layer;
an insulating body extending through the plurality of electrode layers;
a semiconductor layer positioned between the insulating body and the plurality of electrode layers, the semiconductor layer extending along the insulating body;
and
an insulating layer positioned between the semiconductor layer and the plurality of electrode layers, the insulating layer extending along the semiconductor layer,
the insulating body including a first portion extending through the plurality of electrode layers and a second portion positioned between the conductive layer and the first portion, the second portion having a width along the front surface of the conductive layer narrower than a width of the first portion in a same direction, and
the semiconductor layer having a first layer thickness in a direction from the first portion to one of the plurality of electrode layers between the first portion and the one of the plurality of electrode layers, and a second layer thickness in a direction from the second portion to the insulating layer between the second portion and the insulating layer, the first layer thickness being thinner than the second layer thickness.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/463,582Filed 20 Mar 2017 · us provisional application
Priority: 16 Sep 2016
Published: US 2018/0083031 A122 Mar 2018
Granted: 1 May 2018
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

H10B 43/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/10
EEPROM devices comprising charge-trapping gate insulators: characterised by the top-view layout
H10B 43/35
Characterised by the memory core region: with cell select transistors, e.g. NAND
H10W 20/42
Characterised by their conductive parts: vias, e.g. via plugs