Nitride-free spacer or oxide spacer for embedded flash memory

A method, comprising:

• providing a semiconductor substrate;
• forming a pair of select gates over the substrate, the pair of select gates separated from the semiconductor substrate by a select gate dielectric;
• forming a charge-trapping dielectric structure over the pair of select gates and over the semiconductor substrate;
• forming a memory gate over the charge-trapping dielectric structure, the memory gate arranged to an outermost side of a first select gate of the pair of select gates and separated from the semiconductor substrate by the charge-trapping dielectric structure;
• forming a memory gate sidewall spacer along an outer sidewall of the memory gate;
• performing a first etch to remove exposed portions of the charge-trapping dielectric structure from over the semiconductor substrate, wherein the first etch leaves a sidewall recess in the charge-trapping dielectric structure and the sidewall recess undercuts an outer sidewall of the memory gate sidewall spacer;
• forming a conformal oxide or nitride-free layer over the pair of select gates, over the memory gate, and over the memory gate sidewall spacer, the conformal oxide or nitride-free layer extending into the sidewall recess;
• performing a second etch to etch back the conformal oxide or nitride-free layer to leave an oxide spacer or nitride-free spacer in the sidewall recess of the charge-trapping dielectric structure;
• and
• forming a source/drain region in the semiconductor substrate arranged to an outermost sidewall of the oxide spacer or nitride-free spacer.

A method of forming a split gate memory device, comprising:

• forming a pair of select gates over a semiconductor substrate;
• forming a charge-trapping layer over the pair of select gates and over the semiconductor substrate;
• forming a memory gate layer over the charge-trapping layer;
• forming a first insulating memory gate spacer layer over the memory gate layer, and etching back the first insulating memory gate spacer layer and the memory gate layer to form memory gate precursors and first insulating memory gate spacers;
• recessing upper surfaces of the memory gate precursors to expose sidewalls of the charge-trapping layer and to establish memory gates along outermost sidewalls of the pair of select gates;
• forming a second memory gate spacer layer and etching back the second memory gate spacer layer to establish second memory gate spacers along outer sidewalls of the first insulating memory gate spacers and along the exposed sidewalls of the charge-trapping layer;
• performing an etch to remove portions of the charge-trapping layer not covered by the memory gates and the second memory gate spacers, thereby leaving sidewall recesses in the charge-trapping layer under outer sidewalls of the second memory gate spacers;
• and
• forming oxide spacers or nitride-free spacers which extend along outer sidewalls of the second memory gate spacers and which extend into the sidewall recesses in the charge-trapping layer.