Reliable non-volatile memory device

A method for forming a device comprising:

• providing a substrate prepared with a memory cell region;
• and
• forming at least first and second memory cells on the memory cell region, wherein forming each of the memory cells comprises
• forming a split gate having first and second gates, wherein the first gate is a storage gate having a control gate over a floating gate and the second gate is a wordline, wherein forming the split gate comprises forming a floating gate dielectric over and in direct contact with the substrate,
• forming re-oxidized layers which extend from top to bottom of the control gate on sidewalls of the control gate,
• forming control gate spacers on the sidewalls of the control gate,
• forming sacrificial spacers on and in direct contact with the control gate spacers,
• removing the sacrificial spacer which is formed on the control gate spacer on a second gate side of the control gate,
• forming floating gate spacers on sides of the first gate, wherein the floating gate spacer formed on a second gate side of the first gate is in direct contact with the control gate spacer while the floating gate spacer formed on a first or an erase gate side of the first gate is in direct contact with the sacrificial spacer,
• forming a first source/drain (S/D) region adjacent to the second gate and a second S/D region adjacent to the first gate, wherein the first and second gates are coupled in series and the second S/D region being a common S/D region for adjacent first and second memory cells,
• forming a tunneling oxide layer which lines at least sidewalls of the first gates adjacent to the common S/D region and over a top surface of the common S/D region,
• forming an erase gate dielectric over the tunneling oxide layer and over the top surface of the common S/D region, and
• forming an erase gate over the common S/D region, wherein the erase gate is isolated from the common S/D region by the erase gate dielectric, a portion of the tunneling oxide layer and a portion of the floating gate dielectric over the top surface of the common S/D region, wherein a top surface of the erase gate dielectric is below a top surface of the floating gate.