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US 9,960,171 B2Granted
Semiconductor devices including charge storage patterns
AssigneeSamsung Electronics Co., Ltd.
InventorsKohji Kanamori, Shinhwan Kang, Youngwoo Park, Junghoon Park
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Abstract
Semiconductor devices are provided. A semiconductor device includes a plurality of gate electrodes. The semiconductor device includes a channel structure adjacent the plurality of gate electrodes. The semiconductor device includes a plurality of charge storage segments between the channel structure and the plurality of gate electrodes. Methods of forming semiconductor devices are also provided.
Claims15
A semiconductor device, comprising:
- a substrate;
- a gate structure on the substrate, the gate structure comprising gate lines that are stacked on the substrate and spaced apart from each other in a vertical direction;
- a lower insulating pattern between the substrate and the gate structure;
- a channel structure that extends through the gate structure and into the lower insulating pattern;
- charge storage patterns between the channel structure and the gate lines;
- and
- a lower charge storage pattern between the channel structure and the lower insulating pattern,
- wherein the charge storage patterns are spaced apart from each other by first recess regions that are between the gate lines, and
- wherein the lower charge storage pattern is spaced apart from a nearest one of the charge storage patterns by a second recess region that is between the lower insulating pattern and the gate structure.
6 more elements
A semiconductor device, comprising:
- a substrate;
- a lower insulating pattern, a gate structure comprising a plurality of gate lines, and an upper insulating pattern sequentially stacked on the substrate;
- an insulating layer filling spaces between the lower insulating pattern, the gate lines, and the upper insulating pattern;
- a channel structure in the upper insulating pattern, the gate structure, and the lower insulating pattern;
- a lower charge storage pattern between the channel structure and the lower insulating pattern;
- charge storage patterns between the channel structure and the gate lines;
- and
- an upper charge storage pattern between the channel structure and the upper insulating pattern,
- wherein the lower charge storage pattern, the charge storage patterns, and the upper charge storage pattern are vertically spaced apart from each other with the insulating layer interposed therebetween.
6 more elements
Dependencies are inferred from the claim text.