Methods of fabricating memory devices

A method of fabricating a memory device, the method comprising:

• providing a substrate comprising a cell array region and a PMOS region;
• forming a mask pattern comprising a plurality of line-shaped portions that are parallel to each other and extend in a first direction on the cell array region, the mask pattern extending on the PMOS region;
• forming a plurality of grooves that are parallel to each other on the cell array region by etching the substrate using the mask pattern as an etch mask;
• sequentially forming gate dielectric layers, word lines, and capping patterns in the plurality of grooves, respectively;
• removing the mask pattern from the PMOS region to expose the PMOS region, the mask pattern remaining on the cell array region after removing the mask pattern from the PMOS region;
• and
• selectively forming a silicon germanium (SiGe) layer on the PMOS region while using the mask pattern as a barrier to growth of the silicon germanium layer on the cell array region.

A method of forming a memory device, the method comprising:

• forming a mask layer on a substrate that comprises a first region and a second region, the mask layer comprising a first opening exposing the first region and extending on the second region;
• etching the substrate using the mask layer as an etch mask to form a recess in the first region of the substrate;
• forming a word line in the recess;
• removing the mask layer from the second region of the substrate after forming the word line, to expose the second region of the substrate;
• forming an epitaxial layer on the exposed second region of the substrate;
• sequentially forming an insulation layer and a conductive layer on the epitaxial layer;
• and
• patterning the conductive layer to form a gate electrode of a transistor on the epitaxial layer, the epitaxial layer comprising a channel region of the gate electrode of the transistor.