Back to results
US 9,960,168 B2Granted
Capacitor strap connection structure and fabrication method
AssigneeGlobalfoundries Inc.
InventorsVeeraraghavan S. Basker, Kangguo Cheng, Benjamin Ryan Cipriany, Ramachandra Divakaruni, Brian J. Greene, Ali Khakifirooz, Byeong Yeol Kim, William Larsen Nicoll
Life of this patent
Estimating the term…
Abstract
Structures and methods for deep trench capacitor connections are disclosed. The structure includes a reduced diameter top portion of the capacitor conductor. This increases the effective spacing between neighboring deep trench capacitors. Silicide or additional polysilicon are then deposited to complete the connection between the deep trench capacitor and a neighboring transistor.
Claims20
A method of forming a semiconductor structure, comprising:
- forming a cavity in a semiconductor substrate with a semiconductor-on-insulator region disposed over the semiconductor substrate;
- forming a lower portion of a conductor region in the cavity, the lower portion of the conductor region having an upper surface within the cavity;
- forming an annular spacer within the cavity in contact with the upper surface of the lower portion of the conductor region and covering, at least in part, within the cavity-on-insulator layer of the semiconductor-on-insulator region and exposing, at least in part, within the cavity a semiconductor layer of the semiconductor-on-insulator region over the insulator layer;
- forming an upper portion of the conductor region on the lower portion of the conductor region, in part within the annular spacer, in part in contact with the semiconductor layer of the semiconductor-on-insulator region, and in part above a top surface of the annular spacer;
- and
- forming a fin portion out of, at least in part, the upper portion of the conductor region, the fin portion of the conductor region being in contact with the semiconductor layer of the semiconductor-on-insulator region over the semiconductor substrate.
3 more elements
A method of forming a semiconductor structure, comprising:
- forming a cavity in a semiconductor substrate with a semiconductor-on-insulator region disposed over the semiconductor substrate;
- forming a lower portion of a conductor region in the cavity;
- forming an annular nitride liner within the cavity and on the lower portion of the conductor region;
- forming an annular spacer within the annular nitride liner and over, in part, the lower portion of the conductor region;
- forming an upper portion of the conductor region on the lower portion of the conductor region, within the annular spacer;
- recessing the annular spacer to a level below a top surface of the upper portion of the conductor region, wherein the recessed the annular spacer covers, at least in part, within the cavity an insulator layer of the semiconductor-on-insulator region;
- recessing the annular nitride liner to expose within the cavity a semiconductor layer of the semiconductor-on-insulator region;
- forming a silicide region on a top portion of the annular spacer, wherein the silicide region is in contact with the semiconductor layer of the semiconductor-on-insulator region disposed over the semiconductor substrate;
- forming a fin portion from, at least in part, the upper portion of the conductor region, wherein the fin portion is in contact with the silicide region.
6 more elements
A semiconductor structure, comprising:
- a semiconductor substrate;
- a semiconductor-on-insulation disposed on the semiconductor substrate, the semiconductor-on-insulator comprising an insulator layer disposed on the semiconductor substrate and a semiconductor layer disposed in the insulator layer;
- a trench formed within the semiconductor substrate;
- a conductor region disposed in the trench, wherein the conductor region comprises a lower portion comprising a first diameter and an upper portion comprising a second diameter, wherein the second diameter is smaller than the first diameter, and a fin portion formed, at least in part, from the upper portion of the conductor region;
- and
- an annular spacer region disposed around, in part, the upper portion of the conductor region, wherein a portion of the upper portion of the conductor region extends above a top surface of the annular spacer.
3 more elements
Dependencies are inferred from the claim text.