Flipped vertical field-effect-transistor

An integrated circuit comprising:

• at least one vertical transistor, the vertical transistor comprising at least:
• a substrate;
• a first interconnect formed over the substrate;
• a first doped layer situated over the first interconnect;
• at least one fin structure in contact with the first doped layer;
• a dielectric layer in contact with a portion of the fin structure;
• a metal gate layer in contact with the dielectric layer;
• a second doped layer in contact with the fin structure;
• at least a second interconnect formed over the second doped layer;
• and
• a third interconnect in contact with the metal gate layer.

A semiconductor structure comprising at least:

• a substrate;
• a plurality of fin structures;
• a first plurality of interconnects formed over the substrate;
• a first plurality of doped layers situated over the first plurality of interconnects;
• a plurality of dielectric layers, wherein each dielectric layer of the plurality of dielectric layers is in contact with a portion of a fin structure of the plurality of fin structures;
• a metal gate layer formed in contact with the plurality of dielectric layers;
• a second plurality of doped layers, wherein each doped layer of the second plurality of doped layers is in contact with a fin structure of the plurality of fin structures;
• a second plurality of interconnects, wherein each interconnect of the second plurality of interconnects is formed over a doped layer of the second plurality of doped layers;
• an interlayer dielectric formed between each fin structure of the plurality of fin structures;
• and
• an interconnect formed in contact with a portion of the metal gate layer between a pair of fin structures of the plurality of fin structures.