GaN structures
AssigneeNavitas Semiconductor Limited
InventorDaniel M. Kinzer
Life of this patent
Estimating the term…
Abstract
A semiconductor device is disclosed. The device includes a substrate including GaN, a two dimensional electron gas (2DEG) inducing layer on the substrate, and a lateral transistor on the 2DEG inducing layer. The lateral transistor includes source and drain contacts to the 2DEG inducing layer, a gate stack between the source and drain contacts, and a field plate between the gate and the drain contact. The device also includes one or more insulation layers on the 2DEG inducing layer, where the field plate is spaced apart from the 2DEG inducing layer by the insulation layers, and a conductor on the insulation layers, where a first portion of the conductor is spaced apart from the 2DEG inducing layer by the insulation layers by a distance less than 200 nm.
Claims41
A semiconductor device, comprising:
- a substrate comprising GaN;
- a two dimensional electron gas (2DEG) inducing layer on the substrate;
- a lateral transistor on the 2DEG inducing layer, the lateral transistor comprising:
- source and drain contacts to the 2DEG inducing layer,
- a gate stack between the source and drain contacts, and
- a field plate between the gate and the drain contact;
- one or more insulation layers on the 2DEG inducing layer, wherein the field plate is spaced apart from the 2DEG inducing layer by the one or more insulation layers, and
- a capacitor, wherein at least a portion of a plate of the capacitor is formed at the same time and from the same material as the field plate,
- wherein a first portion of the field plate is spaced apart from the 2DEG inducing layer by the one or more insulation layers by a distance less than 200 nm,
- wherein a second portion of the field plate is spaced apart from the 2DEG inducing layer by the one or more insulation layers by a distance greater than 200 nm, and
- wherein at least one of the one or more insulation layers contacts the first portion of the field plate and does not contact the second portion of the field plate.
A semiconductor device, comprising:
- a substrate comprising GaN;
- a two dimensional electron gas (2DEG) inducing layer on the substrate;
- a lateral transistor on the 2DEG inducing layer, the lateral transistor comprising:
- source and drain contacts to the 2DEG inducing layer,
- a gate stack between the source and drain contacts, and
- a field plate between the gate and the drain contact;
- and
- one or more insulation layers on the 2DEG inducing layer, wherein the field plate is spaced apart from the 2DEG inducing layer by the one or more insulation layers, wherein at least one of the one or more insulation layers contacts the 2DEG inducing layer, and wherein at least one of the one or more insulation layers comprises an opening,
- wherein the field plate comprises:
- a first portion in the opening, and wherein the first portion of the field plate contacts the at least one insulation layer which contacts the 2DEG inducing layer, and
- a second portion contacting the one or more insulation layers outside the opening,
- wherein at least one of the one or more insulation layers contacts the first portion of the field plate and does not contact the second portion of the field plate.
A semiconductor device, comprising:
- a substrate comprising GaN;
- a two dimensional electron gas (2DEG) inducing layer on the substrate;
- a lateral transistor on the 2DEG inducing layer, the lateral transistor comprising:
- source and drain contacts to the 2DEG inducing layer,
- a gate stack between the source and drain contacts, and
- a field plate between the gate and the drain contact;
- one or more insulation layers on the 2DEG inducing layer, wherein a first portion of the field plate is spaced apart from the 2DEG inducing layer by the one or more insulation layers, and wherein the first portion of the field plate is configured to substantially prevent electronic conduction in a portion of the 2DEG inducing layer when applied with a potential of 40 V less than the adjacent 2DEG inducing layer,
- wherein a second portion of the field plate is spaced apart from the 2DEG inducing layer by a distance greater than a distance by which the first portion of the field plate is spaced apart from the 2DEG inducing layer;
- and
- a capacitor, wherein a plate of the capacitor is spaced apart from the 2DEG per QS inducing layer by the insulation layer,
- wherein at least one of the one or more insulation layers contacts the first portion of the field plate and does not contact the second portion of the field plate.
An electronic component, comprising:
- a package base;
- and
- at least one GaN-based die secured to the package base and including an electronic circuit comprising:
- a substrate comprising GaN;
- a two dimensional electron gas (2DEG) inducing layer on the substrate;
- a lateral transistor on the 2DEG inducing layer, the lateral transistor comprising:
- source and drain contacts to the 2DEG inducing layer,
- a gate stack between the source and drain contacts, and
- a field plate between the gate and the drain contact;
- one or more insulation layers on the 2DEG inducing layer, wherein the field plate is spaced apart from the 2DEG inducing layer by the one or more insulation layers,
- wherein a first portion of the field plate is spaced apart from the 2DEG inducing layer by the one or more insulation layers by a distance less than 200 nm,
- wherein a second portion of the field plate is spaced apart from the 2DEG inducing layer by the one or more insulation layers by a distance greater than 200 nm, and
- wherein at least one of the one or more insulation layers contacts the first portion of the field plate and does not contact the second portion of the field plate;
- and
- a capacitor, wherein at least a portion of a plate of the capacitor is formed at the same time and from the same material as the field plate of the lateral transistor.
An electronic component, comprising:
- a package base;
- and
- at least one GaN-based die secured to the package base and including an electronic circuit comprising:
- a substrate comprising GaN;
- a two dimensional electron gas (2DEG) inducing layer on the substrate;
- a lateral transistor on the 2DEG inducing layer, the lateral transistor comprising:
- source and drain contacts to the 2DEG inducing layer,
- a gate stack between the source and drain contacts, and
- a field plate between the gate and the drain contact;
- and
- one or more insulation layers on the 2DEG inducing layer, wherein the field plate is spaced apart from the 2DEG inducing layer by the one or more insulation layers, wherein at least one of the one or more insulation layers contacts the 2DEG inducing layer, and wherein at least one of the one or more insulation layers comprises an opening,
- wherein the field plate comprises:
- a first portion in the opening, and wherein the first portion of the field plate contacts the at least one insulation layer which contacts the 2DEG inducing layer, and
- a second portion contacting the one or more insulation layers outside the opening,
- wherein at least one of the one or more insulation layers contacts the first portion of the field plate and does not contact the second portion of the field plate.
An electronic component, comprising:
- a package base;
- and
- at least one GaN-based die secured to the package base and including an electronic circuit comprising:
- a substrate comprising GaN;
- a two dimensional electron gas (2DEG) inducing layer on the substrate;
- a lateral transistor on the 2DEG inducing layer, the lateral transistor comprising:
- source and drain contacts to the 2DEG inducing layer,
- a gate stack between the source and drain contacts, and
- a field plate between the gate and the drain contact;
- one or more insulation layers on the 2DEG inducing layer, wherein a first portion of the field plate is spaced apart from the 2DEG inducing layer by the one or more insulation layers, and wherein the first portion of the field plate is configured to substantially prevent electronic conduction in a portion of the 2DEG inducing layer when applied with a potential of 40 V less than the adjacent 2DEG inducing layer,
- wherein a second portion of the field plate is spaced apart from the 2DEG inducing layer by a distance greater than a distance by which the first portion of the field plate is spaced apart from the 2DEG inducing layer,
- wherein at least one of the one or more insulation layers contacts the first portion of the field plate and does not contact the second portion of the field plate;
- and
- a capacitor, wherein a plate of the capacitor is spaced apart from the 2DEG inducing layer by the one or more insulation layers.
A semiconductor device, comprising:
- a substrate comprising GaN;
- a two dimensional electron gas (2DEG) inducing layer on the substrate;
- a lateral transistor on the 2DEG inducing layer, the lateral transistor comprising:
- source and drain contacts to the 2DEG inducing layer,
- a gate stack between the source and drain contacts, and
- a field plate between the gate and the drain contact;
- one or more insulation layers on the 2DEG inducing layer, wherein the field plate is spaced apart from the 2DEG inducing layer by the one or more insulation layers;
- and
- a diode having a field plate, wherein the field plate of the diode is formed at the same time and from the same material as the field plate of the lateral transistor,
- wherein a first portion of the field plate of the lateral transistor is spaced apart from the 2DEG inducing layer by the one or more insulation layers by a distance less than 200 nm,
- wherein a second portion of the field plate of the lateral transistor is spaced apart from the 2DEG inducing layer by the one or more insulation layers by a distance greater than 200 nm, and
- wherein at least one of the one or more insulation layers contacts the first portion of the field plate of the lateral transistor and does not contact the second portion of the field plate of the lateral transistor.
A semiconductor device, comprising:
- a substrate comprising GaN;
- a two dimensional electron gas (2DEG) inducing layer on the substrate;
- a lateral transistor on the 2DEG inducing layer, the lateral transistor comprising:
- source and drain contacts to the 2DEG inducing layer,
- a gate stack between the source and drain contacts, and
- a field plate between the gate and the drain contact;
- one or more insulation layers on the 2DEG inducing layer, wherein a first portion of the field plate is spaced apart from the 2DEG inducing layer by the one or more insulation layers, and wherein the first portion of the field plate is configured to substantially prevent electronic conduction in a portion of the 2DEG inducing layer when applied with a potential of 40 V less than the adjacent 2DEG inducing layer,
- wherein a second portion of the field plate is spaced apart from the 2DEG inducing layer by a distance greater than a distance by which the first portion of the field plate is spaced apart from the 2DEG inducing layer,
- wherein at least one of the one or more insulation layers contacts the first portion of the field plate and does not contact the second portion of the field plate;
- and
- a diode having a field plate, wherein the field plate of the diode is spaced apart from the 2DEG inducing layer by the one or more insulation layers.
An electronic component, comprising:
- a package base;
- and
- at least one GaN-based die secured to the package base and including an electronic circuit comprising:
- a substrate comprising GaN;
- a two dimensional electron gas (2DEG) inducing layer on the substrate;
- a lateral transistor on the 2DEG inducing layer, the lateral transistor comprising:
- source and drain contacts to the 2DEG inducing layer,
- a gate stack between the source and drain contacts, and
- a field plate between the gate and the drain contact;
- one or more insulation layers on the 2DEG inducing layer, wherein the field plate is spaced apart from the 2DEG inducing layer by the one or more insulation layers,
- wherein a first portion of the field plate is spaced apart from the 2DEG inducing layer by the one or more insulation layers by a distance less than 200 nm,
- wherein a second portion of the field plate is spaced apart from the 2DEG inducing layer by the one or more insulation layers by a distance greater than 200 nm, and
- wherein at least one of the one or more insulation layers contacts the first portion of the field plate and does not contact the second portion of the field plate;
- and
- a diode having a field plate, wherein the field plate of the diode is formed at the same time and from the same material as the field plate of the lateral transistor.
An electronic component, comprising:
- a package base;
- and
- at least one GaN-based die secured to the package base and including an electronic circuit comprising:
- a substrate comprising GaN;
- a two dimensional electron gas (2DEG) inducing layer on the substrate;
- a lateral transistor on the 2DEG inducing layer, the lateral transistor comprising:
- source and drain contacts to the 2DEG inducing layer,
- a gate stack between the source and drain contacts, and
- a field plate between the gate and the drain contact;
- one or more insulation layers on the 2DEG inducing layer, wherein a first portion of the field plate is spaced apart from the 2DEG inducing layer by the one or more insulation layers, and wherein the first portion of the field plate is configured to substantially prevent electronic conduction in a portion of the 2DEG inducing layer when applied with a potential of 40 V less than the adjacent 2DEG inducing layer,
- wherein a second portion of the field plate is spaced apart from the 2DEG inducing layer by a distance greater than a distance by which the first n of the field plate is spaced apart from the 2DEG inducing layer,
- wherein at least one of the one or more insulation layers contacts the first portion of the field plate and does not contact the second portion of the field plate;
- and
- a diode having a field plate, wherein the field plate of the diode is spaced apart from the 2DEG inducing layer by the one or more insulation layers.
Dependencies are inferred from the claim text.