Method for thermo-mechanical stress reduction in semiconductor devices and corresponding device
AssigneeSTMicroelectronics S.r.l.
InventorsPaolo Colpani, Antonella Milani, Lucrezia Guarino, Andrea Paleari
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Abstract
In one embodiment, a semiconductor device includes one or more metallizations, such as, e.g., Cu-RDL metallizations, provided on a passivation layer over a dielectric layer. A via is provided through the passivation layer and the dielectric layer in the vicinity of the corners of the metallization. The via may be a “dummy” via without electrical connections to an active device and may be provided at a distance between approximately 1 micron (10−6 m.) and approximately 10 micron (10−5 m.) from each one of said converging sides landing on an underlying metal layer.
Claims16
A method, comprising:
- manufacturing a semiconductor device, the manufacturing including:
- providing a passivation layer over a dielectric layer, the passivation layer being formed from SiC or silicon carbide (SiC) or silicon nitride (SiN);
- providing a metallization layer on the passivation layer, the metallization layer having a corner;
- and
- providing a via through said passivation layer and said dielectric layer near said corner, a portion of the metallization layer being in the via, wherein the portion of the metallization layer in the via is shaped as a frustum with a base and a tip, wherein thicknesses of the passivation layer and the dielectric layer are such that the tip is farther from a bottom surface of the passivation layer than the base.
The method of claim1, wherein providing said via includes providing the via without electrical connections to an active device.
A semiconductor device, comprising:
- a dielectric layer;
- a passivation layer over the dielectric layer, the passivation layer being an SiC layer or an SiN layer;
- a metallization layer having a corner;
- a plurality of vias including a via through said passivation layer and said dielectric layer near said corner, a portion of the metallization layer being in the via having a frustum shape;
- and
- an underlying metal layer, the underlying metal layer having a plurality of landings underlying the dielectric layer, wherein each portion of the metallization layer in the plurality of vias includes a via landing on the respective landing of the underlying metal layer, wherein the metallization layer is a conductive layer configured to conduct current across the metallization layer, a first one of the plurality of landings being a dummy layer configured to restrict current across the underlying metal layer and a second one of the plurality of landings being an active layer configured to conduct current across the underlying metal layer.
A semiconductor device, comprising:
- a dielectric layer;
- a passivation layer over the dielectric layer, the passivation layer including at least one of SiN and SiC;
- a metallization layer on the passivation layer, the metallization layer having a corner;
- a via through said passivation layer and said dielectric layer near said corner, wherein the metallization layer extends into the via;
- a barrier layer lining the via and extending between the metallization layer and the passivation layer;
- and
- a capping layer over the metallization layer, the capping layer abutting the barrier layer at the corner of the metallization layer.
Dependencies are inferred from the claim text.