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US 9,960,112 B2Granted
Semiconductor device
AssigneeSamsung Electronics Co., Ltd.
InventorsChanho Lee, Hyunsoo Chung, Myeong Soon Park
Life of this patent
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Abstract
A semiconductor device comprising: a substrate; a decoupling capacitor disposed on the substrate; a first connection pad vertically overlapping with the decoupling capacitor; a passivation layer exposing a portion of the first connection pad; and a first solder bump disposed on the first connection pad and covering a portion of a top surface of the passivation layer.
Claims19
A semiconductor device comprising:
- a substrate;
- a decoupling capacitor disposed on the substrate;
- a first connection pad vertically overlapping with the decoupling capacitor;
- a passivation layer having a first opening exposing a portion of the first connection pad through the first opening;
- and
- a first solder bump disposed on the first connection pad and covering a portion of a top surface of the passivation layer,
- wherein the first solder bump fills the first opening and is in contact with the passivation layer.
4 more elements
A semiconductor device comprising:
- a substrate;
- a decoupling capacitor disposed on the substrate;
- a passivation layer having a first opening exposing a first connection pad;
- a first solder bump vertically overlapping with the decoupling capacitor,
- wherein the first solder bump fills the first opening and is in contact with the passivation layer;
- and
- a second solder bump offset from the decoupling capacitor,
- wherein a width of the first solder bump is greater than a width of the second solder bump.
5 more elements
A semiconductor package, comprising:
- a package substrate;
- a semiconductor chip including a decoupling capacitor and a passivation layer, wherein the passivation layer includes a first opening and a second opening;
- a plurality of solder bumps electrically connecting the semiconductor chip to the package substrate;
- wherein the plurality of solder bumps includes
- a first solder bump disposed in the first opening and vertically aligned with the decoupling capacitor, the first solder bump extending over the passivation layer;
- and
- a second solder bump disposed in the second opening, and non-overlapped vertically with a sidewall of the second opening of the passivation layer and the decoupling capacitor.
4 more elements
Dependencies are inferred from the claim text.