Self-enclosed asymmetric interconnect structures
AssigneeIntel Corporation
InventorBoyan Boyanov
Life of this patent
Estimating the term…
Loading patent…
AssigneeIntel Corporation
InventorBoyan Boyanov
Estimating the term…
Techniques are disclosed that enable improved shorting margin between unlanded conductive interconnect features and neighboring conductive features. The techniques provided are particularly useful, for instance, when lithography registration errors cause neighboring conductive features to be physically closer than expected, but can also he used when such proximity is intentional. In some embodiments, the techniques can be implemented using a layer of electromigration management material (EMM) and one or more insulator layers, wherein the various layers are provisioned to enable a differential etch rate. In particular, the overall etch rate of materials above the target landing pad is faster than the overall etch rate of materials above the off-target landing pad, which results in a self-enclosed conductive interconnect feature having an asymmetric taper or profile. The differential etch rate may result, for example, from configuration of the EMM layer, or from accompanying insulator layers having different etch rates.
A semiconductor device, comprising:
A multilayer integrated circuit device, comprising:
A method for forming a semiconductor device, comprising:
Dependencies are inferred from the claim text.