Multiple patterning techniques for metal gate

A method of forming an integrated circuit, comprising:

• forming a high-k dielectric layer over a substrate comprising a first device region, a second device region, a third device region and a fourth device region;
• forming a first work function metal layer directly on the high-k dielectric layer;
• patterning the first work function metal layer to leave a first portion within a first gate region of the first device region and a second portion within a second gate region of the second device region, and to expose the high-k dielectric layer within a third gate region of the third device region and within a fourth gate region of the fourth device region;
• forming a second work function metal layer over the patterned first work function metal layer and exposed high-k dielectric layer;
• and
• patterning the second work function metal layer to leave a first portion within the first gate region and to remove a second portion within the second gate region.

A method of forming an integrated circuit, comprising:

• forming a substrate comprising a first device region, a second device region, and a third device region;
• depositing a high-k dielectric layer over the substrate;
• forming a first work function metal layer directly on the high-k dielectric layer;
• patterning the first work function metal layer to leave a first portion within the first device region and a second portion within the second device region, and to expose the high-k dielectric layer within the third device region;
• forming a cap layer over the first work function metal layer within the first device region and the second device region and over the high-k dielectric layer within the third device region;
• forming a second work function metal layer over the cap layer;
• and
• patterning the second work function metal layer to leave a first portion within the first device region and to remove a second portion within the second device region.