US 9,960,075 B2Granted

Method of manufacturing semiconductor integrated circuit device

AssigneeRenesas Electronics Corporation

InventorsMasaaki Shinohara, Satoshi Iida

Life of this patent

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Abstract

Using an STI insulating film in a high breakdown voltage MOSFET leads to deterioration in reliability due to impact ionization near the bottom corner of a drain isolation insulating film. The invention provides a method of manufacturing a semiconductor integrated circuit device including forming a hard mask film, an opening therein, and a sidewall insulating film on the side surface thereof; forming a shallow trench in the opening with the hard mask film as a mask and oxidizing at least an exposed portion; filling the trench with an insulating film and then removing it so as to leave it outside the trench in the opening and thereby forming a drain offset STI insulating film inside and outside the trench; and forming a gate electrode extending from the upper portion of a gate insulating film in an active region contiguous thereto to the upper portion of the drain offset insulating film.

Claims3

Dependent claims

A semiconductor device comprising:

a substrate having a main surface including a first region and a second region, the first region having a first portion, a second portion, a third portion, a fourth portion and a fifth portion sequentially,
a first trench in the substrate at the second portion;
a first insulation film formed in the first trench;
a second insulation film formed on the first insulation film;
a third insulation film formed on the main surface of the substrate at the fourth portion;
a gate electrode formed on the second insulation film and the third insulation film;
a first semiconductor region formed in the main surface of the substrate at a side of the second insulation film at the first portion;
a second semiconductor region formed in the main surface of the substrate at a side of the gate electrode at the fifth portion;
a second trench in the substrate at the second region;
a fourth insulation film formed in the second trench;
and
a fifth insulation film formed on the fourth insulation film,
wherein the first insulation film and the second insulation film extend on the main surface of the substrate at the third portion, and
wherein the gate electrode is formed over the first insulation film and the second insulation film at the third portion contiguous to the first trench.

11 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/497,740Filed 26 Apr 2017 · continuation
Priority: JP 2014-1358961 Jul 2014
Published: US 2017/0229338 A110 Aug 2017
Granted: 1 May 2018
Term ends: Not estimatedThe source records don’t support an estimate.

Classification26 codes

H10W 10/014
Of isolation regions comprising dielectric materials: using trench refilling with dielectric materials, e.g. shallow trench isolations
H10D 30/0227
Having source and drain regions or source and drain extensions self-aligned to sides of the gate: having both lightly-doped source and drain…
H10D 30/0281
Of double-diffused metal oxide semiconductor [DMOS] FETs: of lateral dmos [ldmos] fets
H10D 30/0285
Of lateral dmos [ldmos] fets: using formation of insulating sidewall spacers

Family

Application14/738,846Parent of this continuation · filed 13 Jun 2015
Application15/053,551Parent of this continuation · filed 25 Feb 2016
US 9,305,824 B2Parent of this continuation · filed 5 Apr 2016
Application15/216,856Parent of this continuation · filed 22 Jul 2016
US 9,418,996 B2Parent of this continuation · filed 16 Aug 2016
US 2017/0229338 A1Pre-grant publication · published 10 Aug 2017
US 9,666,584 B2Parent of this continuation
US 2016/0005640 A1Published application
US 2016/0181246 A1Published application
US 2016/0329330 A1Published application
US 9,960,075 B2This patent

From the US filing history. Foreign family members aren’t listed.