Hard mask removal method
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChe-Hao Tu, William Weilun Hong, Ying-Tsung Chen
Life of this patent
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Abstract
A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP.
Claims20
A method of removing a hard mask, the method comprising:
- patterning a plurality of gate stacks on a substrate so as to include a first set of gate stacks in an isolated region and a second set of gate stacks in a dense region, wherein each gate stack of the first set has smaller pattern features in a dimension of a lateral linewidth than does each gate stack of the second set, wherein each gate stack of the plurality of gate stacks includes a polysilicon layer, the hard mask being deposited over the polysilicon layer of each gate stack;
- depositing a dielectric layer directly on regions of the substrate between the gate stacks of the patterned plurality of gate stacks and directly on the patterned plurality of gate stacks, a first portion of the deposited dielectric layer having a greater thickness over the first set of gate stacks than a second portion of the deposited dielectric layer over the second set of gate stacks;
- planarizing the first portion of the deposited dielectric layer over the first set of gate stacks by chemical mechanical polishing (CMP) to remove the greater thickness of the dielectric layer over the first set of gate stacks;
- continuing the CMP to remove the hard mask from each gate stack of the plurality of gate stacks and remove the second portion of the dielectric layer;
- and
- after the CMP, substantially removing a remaining portion of the dielectric layer over the regions of the substrate between the gate stacks of the patterned plurality of gate stacks.
A method of planarizing gate stacks disposed on a substrate, each gate stack of a first plurality of the gate stacks in an isolated region being laterally smaller than each gate stack of a second plurality of the gate stacks in a dense region, each gate stack including a polysilicon layer and a hard mask disposed on the polysilicon layer, the method comprising:
- depositing a dielectric layer in direct contact with the hard mask of each gate stack, the dielectric layer being thicker in the isolated region than in the dense region;
- and
- applying chemical mechanical polishing (CMP) to completely remove the dielectric layer over the hard mask of each gate stack of the second plurality of gate stacks and to partially remove the dielectric layer over the hard mask of each gate stack of the first plurality of gate stacks;
- and
- continuing the CMP to completely remove the hard masks of the gate stacks of the second plurality of gate stacks and to completely remove the dielectric layer over the hard mask of each gate stack of the first plurality of gate stacks.
A method of planarizing gate stacks disposed on a substrate, each gate stack of a first plurality of the gate stacks in an isolated region being laterally smaller than each gate stack of a second plurality of the gate stacks in a dense region, each gate stack including a polysilicon layer and a hard mask disposed on the polysilicon layer, the method comprising:
- depositing a dielectric layer in direct contact with the hard mask of each gate stack, the dielectric layer being thicker in the isolated region than in the dense region;
- applying chemical mechanical polishing (CMP) to completely remove the dielectric layer over the hard mask of each gate stack of the second plurality of gate stacks and to partially remove the dielectric layer over the hard mask of each gate stack of the first plurality of gate stacks;
- and
- continuing the CMP to partially remove the polysilicon layers of the gate stacks of the second plurality of gate stacks and to completely remove the hard masks of the gate stacks of the first plurality of gate stacks.
Dependencies are inferred from the claim text.