Granular cache repair
AssigneeIntel Corporation
InventorsBahaa Fahim, Min Huang, Zhiguo Wang
Life of this patent
Estimating the term…
Abstract
Systems and methods for granular cache repair. An example processing system comprises a processing core communicatively coupled to a cache via a cache controller and a cache repair memory communicatively coupled to the cache controller. The cache controller is configured, responsive to receiving a read request referencing a physical address, to: retrieve cache data from a cache location identified by the physical address, retrieve, in parallel with retrieving the cache data, cache repair data from the cache repair memory, the cache repair data associated with the cache location, the cache repair data comprising at least one of: a bit repair value, a column repair value, and a raw repair value, and output the cache data multiplexed with the cache repair data.
Claims18
A processing system, comprising:
- a processing core communicatively coupled to a cache via a cache controller;
- a cache repair memory communicatively coupled to the cache controller;
- wherein the cache controller is configured, responsive to receiving a read request referencing a physical address, to:
- retrieve cache data from a cache location identified by the physical address,
- retrieve, from the cache repair memory a bit repair value associated with a specific bit of the cache location, a column repair value associated with a specific column of the cache location, and a row repair value associated with the a specific row of cache location,
- produce cache repair data by multiplexing the bit repair value, the column repair value, and the row repair value, and
- output the cache data multiplexed with the cache repair data.
A method, comprising:
- receiving, by a processing system, a cache read request referencing a physical address;
- retrieving cache data from a cache location identified by the physical address;
- retrieving, from the cache repair memory a bit repair value associated with a specific bit of the cache location, a column repair value associated with a specific column of the cache location, and a row repair value associated with a specific row of the cache location;
- producing cache repair data by multiplexing the bit repair value, the column repair value, and the row repair value;
- and
- outputting the cache data multiplexed with the cache repair data.
A system-on-chip (SoC), comprising:
- a system memory;
- a cache to store contents of at least a subset of the system memory in the cache;
- a cache controller communicatively coupled to the cache;
- a cache repair memory communicatively coupled to the cache controller;
- a processing core communicatively coupled to the memory and to the cache controller;
- wherein the cache controller is configured, responsive to receiving a read request referencing a physical address, to:
- retrieve cache data from a cache location identified by the physical address,
- retrieve, from the cache repair memory a bit repair value associated with a specific bit of the cache location, a column repair value associated with a specific column of the cache location, and a row repair value associated with the a specific row of cache location,
- produce cache repair data by multiplexing the bit repair value, the column repair value, and the row repair value, and
- output the cache data multiplexed with the cache repair data.
Dependencies are inferred from the claim text.