Memory system including test circuit

A method for testing a memory system including a semiconductor memory device, the method comprising:

• transmitting serial test data and control data through one of a plurality of first pins of the memory system, the plurality of first pins conforming to the a first interface protocol;
• converting, in the memory system, the serial test data to parallel test data;
• when the control data indicates to assert a control signal on one of a plurality of second pins conforming to a second interface protocol, a number of the first pins being smaller than a number of second pins, writing the parallel test data in the semiconductor memory device;
• reading the parallel test data written in the semiconductor memory device;
• converting the read parallel test data to serial test data;
• receiving, from the memory system, the serial test data that has been converted from the read parallel test data;
• and
• comparing the transmitted serial test data and the received serial test data.

A memory system, comprising:

• a semiconductor memory device;
• a plurality of first pins for connection to the outside of the memory system, the first pins conforming to a first interface protocol and configured to receive and output serial data;
• a plurality of second pins conforming to a second interface protocol, a number of the first pins being smaller than a number of second pins;
• a first serial/parallel conversion circuit configured to convert first serial data in a first data sequence format, which are received through one of the first pins, to first parallel data for writing in the semiconductor memory device, when the memory system operates in a first mode;
• and
• a second serial/parallel conversion circuit configured to convert second serial data in a second data sequence format, which are received through one of the first pins, to second parallel data for writing in the semiconductor memory device, when the memory system operates in a second mode.