Input-output circuit for supporting multiple-input shift register (MISR) function and memory device including the same

An integrated circuit device, comprising:

• an input/output (IO) circuit having a reception circuit and a register circuit therein, said reception circuit configured support both normal write and test write modes, generate a plurality of latch signals and receive a plurality of input signals, and said register circuit configured to generate a plurality of test result signals in response to the plurality of latch signals when said reception circuit is disposed in the test write mode;
• wherein said reception circuit comprises:
• a plurality of sampling circuits configured to generate a corresponding plurality of sampled signals by sampling data signals received by said I/O circuit in-sync with a write data strobe signal;
• and
• a plurality of latch circuits configured to latch the plurality of sampled signals in-sync with a write master clock signal;
• wherein each of said plurality of sampling circuits is configured to generate rising sampled signals by sampling corresponding data signals in-sync with rising edges of the write data strobe signal and generate falling sampled signals by sampling the corresponding data signals in-sync with falling edges of the write data strobe signal;
• and
• wherein each of said plurality of latch circuits is configured to generate rising latch signals by latching each of the rising sampled signals in-sync with the write master clock signal and generate falling latch signals by latching each of the falling sampled signals in-sync with the write master clock signal.

An input-output circuit comprising:

• a reception circuit configured to operate in accordance with a normal write protocol commonly in a normal write mode and a test write mode and configured to receive a plurality of input signals to generate a plurality of latch signals;
• and
• a register circuit configured to generate a plurality of test result signals based on the latch signals in the test write mode,
• wherein the reception circuit generates the plurality of latch signals in synchronization with a write master clock signal that is generated based on a write latency and a burst length in accordance with the normal write protocol, and
• wherein the register circuit generates the plurality of test result signals in synchronization with a test clock signal that is a delayed version of the write master clock signal.