High-speed differential current sensing of preprogrammed NVM cells

#This invention relates to the sensing of NVM (Non-Volatile Memory) semiconductor cells and, in particular, sensing the NVM memory cells by differential pair current sensing techniques.

#There are many types of NVM semiconductor cells, such as ROM (Read-Only Memory), EPROM (Erasable ROM), EEPROM (Electrically Erasable ROM), flash memory and OTP (One-Time Programmable) cells. In a NVM memory, the conventional sensing technique is a single-ended with the voltage developed on a selected bit line compared to an analog reference voltage. That is, to read the data in a selected NVM memory cell, only a single line, the bit line, from the NVM memory cell is used to sense the data in the NVM memory cell in a reading operation.

#On the other hand, in some of the assignee's applications the bit line and its complementary bit line of the selected NVM memory cells are differentially sensed. That is, in the programming of a selected memory cell there are two possibilities: that the cell connected to the bit line is to be programmed or a related cell connected to the complementary bit line is to be programmed. Hence to read the contents of a memory cell at a particular address, there are two available memory cells, each with complementary programmed states. This allows for current differential sensing, such as found in SRAM (Static Random Access Memory) integrated circuits, in which the sense amplifier of cross-coupled inverter circuits permit the complementary states of the selected memory cell and its complement to pull the sense amplifier into one state or its complementary state quickly.

#FIG. 1 shows the differential sensing circuit architecture of one embodiment of the present invention.

#FIG. 2 shows various signal waveforms and their timing for the FIG. 1 circuit architecture.

#FIG. 1 shows the circuit architecture of one embodiment of the present invention. A block 10 of NVM memory cells is connected to a sense amplifier 20 by a bit line 31A and its complementary bit line 31B through PMOS transistors 13A and 13B respectively. Through the bit lines 31A and 31B, the sense amplifier 10 drives an output latch/logic block 40. Various control lines 51-56, including those from a control logic block 41, handle and time the current sensing operations and are described below. All of these elements are part of an integrated circuit implemented in standard CMOS technology.

#The memory block 10 has a plurality of NVM, specifically OTP (One-Time Programmable), memory cells. Memory cell 11A represents the cells connected to the bit line 31A and memory cell 11B represents the cells connected to the complementary bit line 31B. Each of the memory cells 11A, 11B is also connected to word lines, word line WP 32 and word line WR 33. The word line 33, which is connected to the gate of the pass transistor of the memory cells 11A and 11B, addresses the selected cell for a read operation and the word line 32, which is connected to the gate of the programming element of the cells 11A, 11B, is also engaged for programming the selected cell. The OTP cells in the memory block 10 are programmed so that one of two memory cells, a memory cell 11A connected to a bit line 31A and its complementary cell 11B connected to the complementary bit line 31B, is programmed. How the particular memory cell is selected is beyond the scope of this invention.

#In a normal read operation, i.e., an operation to sense the state of a programmed cell, the word line 33 addresses a memory cell 11A and its complementary cell 11B. As stated earlier, only one of the cells is the “actual” addressed cell and only one of the cells is programmed. The input/outputs of the sense amplifier 20 are connected to the bit line 13A and complementary bit line 31B. As is well understood by circuit designers, the cross-coupled inverter circuits of the sense amplifier 20 respond to the differential in the currents (and voltages) on the bit line 31A and complementary bit line 31B by flipping into one state or another. That is, the bit line current differential causes one of the logic inverters into a “1” state and the other logic inverter into a “0” state.