Non-volatile memory devices and methods of operating the same
AssigneeSamsung Electronics Co., Ltd.
InventorsHo-Jun Lee, Sang-Hyun Joo
Life of this patent
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Abstract
A method of operating a non-volatile memory device includes selecting a first select transistor from among a plurality of select transistors included in a NAND string, and performing a check operation on a first threshold voltage of the first select transistor. The check operation includes comparing the first threshold voltage with a first lower-limit reference voltage level, and performing a program operation on the first select transistor when the first threshold voltage is lower than the first lower-limit reference voltage level. When the first threshold voltage is equal to or higher than the first lower-limit reference voltage level, the check operation on the first threshold voltage is ended.
Claims4
A method of operating a non-volatile memory device including first and second memory planes independently controllable of one another, wherein each of the first and second memory planes includes a plurality of memory blocks, and each of the plurality of memory blocks includes a plurality of NAND strings, the method comprising:
- selecting a first select transistor from among a plurality of select transistors included in a first NAND string of a first memory block of each of the first and second memory planes;
- checking whether a first threshold voltage of the first select transistor of each of the first and second memory planes is within a first reference voltage range;
- processing the first memory block of the first memory plane as a bad block when the first threshold voltage of the first select transistor of the first memory plane is not within the first reference voltage range;
- and
- processing the first memory block of the second memory plane as a bad block when the first threshold voltage of the first select transistor of the second memory plane is not within the first reference voltage range,
- wherein when both the first memory block of the first memory plane and the first memory block of the second memory plane are processed as bad blocks, a check operation on the remaining select transistors from among the plurality of select transistors is skipped.
Dependencies are inferred from the claim text.