Grouping memory cells into sub-blocks for program speed uniformity

A memory device, comprising:

• a plurality of word line layers which are vertically spaced apart from one another by dielectric layers;
• a set of NAND strings extending through the plurality of word line layers, the set of NAND strings comprises NAND strings in an interior sub-block of a block region, NAND strings in a first edge portion of the block region and NAND strings in a second edge portion of the block region, wherein the interior sub-block is between the first and second edge portions;
• a first set of bit lines connected to the NAND strings of the first edge portion and the NAND strings of the interior sub-block but not to the NAND strings of the second edge portion;
• and
• a second set of bit lines connected to the NAND strings of the second edge portion and the NAND strings of the interior sub-block but not to the NAND strings of the first edge portion, wherein a thickness of a block oxide layer in the NAND strings of the first and second edge portions is less than a thickness of a block oxide layer in the NAND strings of the interior sub-block.