Method and apparatus for selective write assist using shared boost capacitor

A memory device, comprising:

• a plurality of memory cells arranged into a plurality of rows and a plurality of columns;
• a row decoder configured to access a row from among the plurality of rows;
• a column decoder configured to access a column of the row from among the plurality of columns to select a memory cell from among the plurality of memory cells;
• column circuitry configured to write data to the selected memory cell, the column circuitry comprising:
• a plurality of write assist circuits coupled to the plurality of memory cells;
• a shared boost capacitor shared by the plurality of write assist circuits, the shared boost capacitor having a first terminal and a second terminal;
• and
• a boost switch circuit configured to selectively couple a write assist circuit corresponding to the selected memory cell from among the plurality of write assist circuits to the first terminal of the shared boost capacitor to provide write assistance to the selected memory cell,
• wherein the boost switch circuit comprises;
• a logic gate connected to the second terminal of the shared boost capacitor, the logic gate being configured to:
• receive an input from each one of the plurality of write assist circuits resulting in a plurality of inputs, and
• toggle a voltage on the second terminal of the shared boost capacitor to generate a negative voltage on the first terminal of the shared boost capacitor in response to the plurality of inputs indicating one or more first memory cells from among the plurality of columns of memory cells need write assistance;
• and
• a plurality of write assist enable transistors, each write assist enable transistor corresponding to one of the plurality of write assist circuits and independently controllable by a corresponding write assist control line, each write assist enable transistor configured to selectively connect and disconnect the negative voltage on the first terminal of the shared boost capacitor to bitlines of the corresponding write assist circuit based on a control signal on the corresponding write assist control line;
• wherein the selectively coupled write assist circuit is configured to cause the selected memory cell to change its logical state during a write operation using the negative voltage.

A method of writing data to a memory cell from among a plurality of memory cells, the plurality of memory cells being arranged into a plurality of rows and a plurality of columns, the method comprising:

• accessing a row from among the plurality of rows;
• accessing a column of the row from among the plurality of columns to select the memory cell;
• selectively coupling, by a write assist enable transistor, a write assist circuit corresponding to the memory cell from among the plurality of write assist circuits to a first terminal of a shared boost capacitor to provide write assistance to the memory cell, the shared boost capacitor being shared by the plurality of write assist circuits;
• receiving by a logic gate connected to the shared boost capacitor, a plurality of inputs corresponding to the plurality of write assist circuits;
• toggling, by the logic gate, a voltage on the second terminal of the shared boost capacitor to generate a negative voltage on the first terminal of the shared boost capacitor in response to the plurality of inputs indicating one or more first memory cells from among the plurality of columns of memory cells need write assistance;
• and
• writing data to the memory cell utilizing the write assistance, the writing comprising:
• causing the memory cell to change its logical state during a write operation using the negative voltage.