Semiconductor integrated circuit device and wearable device

A semiconductor integrated circuit device comprising:

• a first circuit that includes a P-type MOS transistor and an N-type MOS transistor;
• a mode designation circuit that designates an operation speed of the first circuit;
• a second circuit that includes a P-type SOTB transistor and an N-type SOTB transistor and is connected to the first circuit;
• a first voltage supply circuit which supplies a first voltage;
• a second voltage supply circuit which supplies a second voltage;
• a third voltage supply circuit which supplies a third voltage;
• and
• a fourth voltage supply circuit which supplies a fourth voltage,
• wherein the first voltage supply circuit supplies the first voltage to a substrate of the P-type SOTB transistor and the second voltage supply circuit supplies the second voltage to a substrate of the N-type SOTB transistor when the mode designation circuit designates a first operation mode to operate the first circuit at a first speed, and
• wherein the third voltage circuit supplies the third voltage to a substrate of the P-type MOS transistor and the fourth voltage supply circuit supplies the fourth voltage to a substrate of the N-type MOS transistor when the mode designation circuit designates the first operation mode,
• wherein the third voltage differs from the first voltage and the fourth voltage equals to the second voltage,
• wherein the first and second voltage supply circuits do not supply the first and second voltages when the mode designation circuit designates a second operation mode to operate the first circuit at a second speed higher than the first speed,
• wherein the second circuit is a static memory which includes a plurality of memory cells,
• wherein each of the plurality of memory cells includes a pair of inverter circuits composing a flip flop circuit, which is configured by the P-type SOTB transistor and the N-type SOTB transistor, and
• wherein, when an absolute value of a threshold voltage of the P-type SOTB transistor in the pair of inverter circuits is equal to an absolute value of a threshold voltage of the N-type SOTB transistor in the pair of inverter circuits, the first and the second voltage supply circuit supply the first and second voltages, respectively, in the first operation mode such that the absolute value of the threshold voltage of the P-type SOTB transistor in the pair of inverter circuits is higher than the absolute value of the threshold voltage of the N-type SOTB transistor in the pair of inverter circuits.