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US 9,959,919 B2Granted
Memory system including non-volatile memory of which access speed is electrically controlled
AssigneeKabushiki Kaisha Toshiba
InventorsDaisuke Saida, Susumu Takeda, Hiroki Noguchi, Kazuhiko Abe
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Abstract
A memory system has a non-volatile memory of which access speed is electrically controlled, a control circuitry that selects a first region which is a portion of a memory region of the non-volatile memory, and a boost circuit that adjusts an access speed of the first region to be higher than an access speed of a second region different from the first region in the memory region.
Claims19
A memory system comprising:
- a non-volatile memory of which access speed is electrically controlled;
- first circuitry that selects a first region which is a portion of a memory region of the non-volatile memory;
- and
- second circuitry that adjusts an access speed of the first region to be higher than an access speed of a second region different from the first region in the memory region,
- wherein the first circuitry selects the first region on the basis of at least one of a frequency of access, and an access history.
2 more elements
A memory system comprising:
- a non-volatile memory of which access speed is electrically controlled;
- first circuitry that selects a first region which is a portion of a memory region of the non-volatile memory;
- and
- second circuitry that adjusts an access speed of the first region to be higher than an access speed of a second region different from the first region in the memory region,
- wherein the first circuitry selects the first region on the basis of at least one of a latency of a processor, an endurance of the non-volatile memory, a frequency of access, and an access history,
- wherein the second circuitry changes the access speed of the first region from a first speed to a second speed faster than the first speed, and after a predetermined period of time elapses, returns the access speed of the first region from the second speed to the first speed.
3 more elements
A memory system comprising:
- a non-volatile memory of which access speed is electrically controlled;
- first circuitry that selects a first region which is a portion of a memory region of the non-volatile memory;
- and
- second circuitry that adjusts an access speed of the first region to be higher than an access speed of a second region different from the first region in the memory region,
- wherein the first circuitry selects the first region on the basis of at least one of a latency of a processor, an endurance of the non-volatile memory, a frequency of access, and an access history,
- wherein the first regions is closer to a processor than the second region.
3 more elements
A memory system comprising:
- a non-volatile memory of which access speed is electrically controlled;
- first circuitry that selects a first region which is a portion of a memory region of the non-volatile memory;
- and
- second circuitry that adjusts an access speed of the first region to be higher than an access speed of a second region different from the first region in the memory region,
- wherein the first region comprises a plurality of sub-regions, and
- the second circuitry adjusts such that the access speeds of the plurality of sub-regions are different from one another.
3 more elements
A memory system comprising:
- a non-volatile memory of which access speed is electrically controlled;
- first circuitry that selects a first region which is a portion of a memory region of the non-volatile memory;
- and
- second circuitry that adjusts an access speed of the first region to be higher than an access speed of a second region different from the first region in the memory region,
- wherein the first circuitry is permitted to select a plurality of the first regions, and
- when the first circuitry selects the plurality of first regions, the second circuitry adjusts the access speed of each of the plurality of first regions to be higher than the access speed of the second region.
3 more elements
A memory system comprising:
- a non-volatile memory of which access speed is electrically controlled;
- first circuitry that selects a first region which is a portion of a memory region of the non-volatile memory;
- and
- second circuitry that adjusts an access speed of the first region to be higher than an access speed of a second region different from the first region in the memory region,
- wherein the first circuitry selects the first region on the basis of at least one of a latency of a processor, an endurance of the non-volatile memory, a frequency of access, and an access history,
- wherein the second circuitry adjusts a voltage in the first region to be higher than a voltage in the second region.
3 more elements
Dependencies are inferred from the claim text.