Memory device and system supporting command bus training, and operating method thereof

A command bus training method in a system in which a command/address signal and a clock signal are provided to a memory device from a memory controller, the command bus training method comprising:

• generating a plurality of internal clock signals in the memory device by dividing the clock signal;
• transmitting a first command/address signal by the memory controller;
• transmitting a chip selection signal by the memory controller, the chip selection signal having an adjustable delay with respect to each of the internal clock signals;
• generating a plurality of internal chip selection signals in the memory device by latching the chip selection signal according to the plurality of internal clock signals;
• generating and transmitting by the memory device, a second command/address signal by encoding the first command/address signal based on the plurality of internal chip selection signals;
• and
• determining a delay of the chip selection signal based on the first and second command/address signals in the memory controller.

A method of command bus training for a semiconductor device, the method comprising:

• receiving a first command/address signal, and a clock signal having a first frequency;
• generating internal clock signals based on the clock signal, each of the internal clock signals having a second frequency and different phases with respect to each other, wherein the second frequency is smaller than the first frequency;
• a) receiving a chip selection signal having variable delays with respect to each of the internal clock signals;
• b) generating internal chip selection signals by latching the chip selection signal based on the internal clock signals;
• c) generating a second command/address signal by encoding the first command/address signal based on the internal chip selection signals;
• and
• determining a delay of the chip selection signal based on the first and second command/address signals.