Memory controller integrated circuit with multiple request ports and link calibration support
AssigneeRambus Inc.
InventorsRichard E. Perego, Frederick A. Ware
Life of this patent
Estimating the term…
Abstract
A memory system includes a memory controller with multiple command/address ports and a memory device having corresponding request ports. The memory controller issues commands to memory device to cause the memory device to “loop-back” signals conveyed to memory device over one of the command/address ports via a bidirectional data link; these signals can be deterministic test patterns. The memory controller compares the returned information with the originally transmitted patterns to perform calibration. In one embodiment, because the return links are already calibrated, errors can be attributed to issues in the forward links; the memory controller then adjusts timing of the forward links to minimize the errors.
Claims20
An integrated circuit having a memory controller to control the operation of a dynamic random access memory (“DRAM”) device, the DRAM device having at least two request ports, the integrated circuit comprising:
- a request interface having at least two command/address ports, each command/address port to send write commands and corresponding addresses to a respective one of the at least two request ports of the DRAM device, and each command/address port to send at least one test pattern to the respective one of the at least two request ports;
- and
- a plurality of bidirectional data interfaces to send data corresponding to the write commands to the DRAM device and to receive back from the DRAM device information based on the test patterns which were sent by the at least two command/address ports to the at least two request ports.
A method of operating a memory controller to control the operation of a dynamic random access memory (“DRAM”) device, the DRAM device having at least two request ports, the method comprising:
- causing each of at least two command/address ports of a request interface to send write commands and corresponding addresses to a respective one of the at least two request ports of the DRAM device;
- causing each of the at least two command/address ports to send at least one test pattern to the respective one of the at least two request ports;
- using a plurality of bidirectional data interfaces to send data corresponding to the write commands to the DRAM device;
- and
- receiving back from the DRAM device via the plurality of bidirectional data interfaces information based on the test patterns which were sent to the at least two request ports of the DRAM device.
An integrated circuit comprising a memory controller to control the operation of a dynamic random access memory (“DRAM”) device, the DRAM device having at least two request ports, the apparatus further comprising:
- means for causing each of at least two command/address ports of a request interface to send write commands and corresponding addresses to a respective one of the at least two request ports of the DRAM device and for causing each of the at least two command/address ports to send at least one test pattern to the respective one of the at least two request ports;
- and
- means for using a plurality of bidirectional data interfaces to send data corresponding to the write commands to the DRAM device, and for receiving back from the DRAM device via the plurality of bidirectional data interfaces information dependent on the test patterns which were sent to the at least two request ports of the DRAM device.
Dependencies are inferred from the claim text.