Timed sense amplifier circuits and methods in a semiconductor memory

A method for operating a memory, comprising:

• enabling a sense amplifier in a read operation by a timing circuit, the sense amplifier being coupled to at least one bitline, and the at least one bitline being coupled to a memory cell;
• enabling the sense amplifier for an extended time period longer than a period for the read operation independent of the timing circuit in a second operation;
• pulling up the at least one bitline by a pull-up circuit while the sense amplifier is enabled in the second operation;
• and
• determining whether the sense amplifier changes states during the extended enabling period.

A memory, comprising:

• a plurality of memory cells;
• a plurality of wordlines respectively coupled to the plurality of memory cells;
• at least one bitline coupled to one memory cell of the plurality of memory cells;
• a sense amplifier coupled to the at least one bitline;
• a control circuit configured to enable the sense amplifier for an extended time period longer than a period for a read operation and determine whether the sense amplifier changes states during the extended enabling period;
• and
• an address decoder configured to assert the plurality of wordlines while the sense amplifier is enabled by the control circuit.

An apparatus, comprising:

• a plurality of memory cells;
• a plurality of wordlines respectively coupled to the plurality of memory cells;
• at least one bitline coupled to one memory cell of the plurality of memory cells;
• sense amplifying means for sensing data on the at least one bitline;
• timing means for enabling the sense amplifier means during a read operation;
• control means for enabling the sense amplifying means independent of the timing circuit means for an extended time period longer than a period for the read operation and determine whether the sense amplifier changes states during the extended enabling period;
• and
• address decoding means for asserting the plurality of wordlines.