Memory array and method of forming the same

A memory array comprising:

• a first conductive layer comprising:
• a first bit line;
• a second bit line;
• and
• a third bit line;
• a first pre-charge circuit coupled to the first bit line;
• a second pre-charge circuit coupled to the second bit line;
• a first column of memory cells comprising:
• the first bit line;
• the second bit line;
• and
• a first word line;
• and
• a second column of memory cells comprising:
• the second bit line;
• the third bit line;
• and
• a second word line,
• wherein the first column of memory cells and the second column of memory cells are configured to share the second bit line;
• at least two of the first bit line, the second bit line or the third bit line are in a first plane;
• and
• the first word line and the second word line are in a second plane, the second plane intersecting the first plane.

A method comprising:

• forming a first column of memory cells comprising:
• a first bit line;
• a first word line;
• and
• a second bit line, the first bit line and the second bit line being in a first plane;
• forming a second column of memory cells comprising:
• the second bit line;
• a second word line, the first word line and the second word line being in a second plane intersecting the first plane;
• and
• a third bit line;
• sharing the second bit line between the first column of memory cells and the second column of memory cells;
• and
• sharing a set of memory array elements between the first column of memory cells and the second column of memory cells, the set of memory array elements comprising:
• a first bit line pre-charge circuit coupled to the first bit line;
• and
• a second bit line pre-charge circuit coupled to the second bit line.