Clock and data recovery circuit detecting unlock of output of phase locked loop

A clock and data recovery circuit comprising:

• a phase locked loop configured to receive a data stream into which an additional bit is inserted at every reference period to generate parallelized data and a clock signal;
• a first detector circuit configured to determine whether the parallelized data is locked based on a bit-conversion of the data stream according to an insertion of the additional bits;
• and
• a second detector circuit configured to determine whether the parallelized data is locked based on a control voltage output from the phase locked loop,
• wherein the bit-conversion is executed with respect to the additional bits according to a predetermined protocol, or is executed with respect to at least one bit from among data of the data stream located between a current one of the additional bits and a next one of the additional bits.

A display apparatus driving circuit comprising:

• a timing controller configured to insert an additional bit periodically into received image data to generate modified image data, generate a data stream including the modified image data, and output the data stream;
• and
• a source driver configured to receive the data stream, the source driver comprising:
• a phase locked loop configured to generate parallelized data and a clock signal from the received data stream;
• and
• a detector circuit configured to determine whether the parallelized data is locked based on values of the additional bits in the received data stream.