Display device and method for driving same with light-emission enable signal switching unit

An active matrix-type display device that performs color image display by dividing one frame period into j subframes (j is an integer greater than or equal to 3) and displaying different color screens in different subframes, the active matrix-type display device comprising:

• pixel circuits arranged in a matrix form so as to form a plurality of rows and a plurality of columns, each of the pixel circuits including:
• j electro-optical elements configured to emit light of different colors respectively;
• a drive current control unit configured to control a drive current for bringing the j electro-optical elements into a light-emitting state;
• and j light-emission control transistors configured to control supply of the drive current to their corresponding electro-optical elements, the j light-emission control transistors being provided in a one-to-one correspondence with the j electro-optical elements;
• a light-emission enable signal generating unit configured to generate a light-emission enable signal for controlling on/off states of the j light-emission control transistors;
• j light-emission control lines provided for each row, the j light-emission control lines being configured to supply the light-emission enable signal to the j light-emission control transistors;
• a light-emission enable signal switching unit configured to switch a supply destination of the light-emission enable signal among the j light-emission control lines in each row, such that the light-emission enable signal is supplied to different light-emission control lines in different subframes, the light-emission enable signal being generated by the light-emission enable signal generating unit;
• and
• a unit circuit;
• wherein the light-emission enable signal switching unit includes:
• a first control signal generating unit configured to generate a first control signal;
• and
• j light-emission enable signal supply control transistors provided for each row in a one-to-one correspondence with the j light-emission control lines,
• wherein the first control signal is provided to control terminals of the j light-emission enable signal supply control transistors,
• first conduction terminals of the j light-emission enable signal supply control transistors are connected to the light-emission enable signal generating unit,
• second conduction terminals of the j light-emission enable signal supply control transistors are connected to their corresponding light-emission control lines,
• the first control signal generating unit generates the first control signal such that one of the j light-emission enable signal supply control transistors goes into an on state in each subframe, and each of the j light-emission enable signal supply control transistors goes into an on state once during one frame period;
• wherein the light-emission enable signal generating unit includes a shift register having a plurality of stages,
• the shift register outputs the light-emission enable signals to the plurality of rows based on a plurality of clock signals inputted from an external source, the light-emission enable signals sequentially going to an on level;
• wherein the unit circuit forming each of the stages of the shift register includes:
• a first node;
• a first output node configured to output an other-stage control signal that controls operation of a unit circuit of a different stage;
• a second output node configured to output the light-emission enable signal;
• a first transistor having:
• a control terminal to which the other-stage control signal outputted from a unit circuit of a previous stage is provided;
• a first conduction terminal to which the other-stage control signal is provided;
• and a second conduction terminal connected to the first node;
• a second transistor having:
• a control terminal connected to the first node;
• a first conduction terminal to which one of the plurality of clock signals is provided;
• and a second conduction terminal connected to the first output node;
• a third transistor having:
• a control terminal connected to the first node;
• a first conduction terminal to which an on-level direct-current power supply voltage is provided;
• and a second conduction terminal connected to the second output node;
• a fourth transistor having:
• a control terminal to which the other-stage control signal outputted from a unit circuit of a subsequent stage is provided;
• a first conduction terminal connected to the first output node;
• and a second conduction terminal to which an off-level direct-current power supply voltage is provided;
• a fifth transistor having:
• a control terminal to which the other-stage control signal outputted from the unit circuit of the subsequent stage is provided;
• a first conduction terminal connected to the first node;
• and a second conduction terminal to which an off-level direct-current power supply voltage is provided;
• and
• a sixth transistor having:
• a control terminal to which a subframe reset signal is provided, the subframe reset signal going to an on level at an end time point of each subframe;
• a first conduction terminal connected to the second output node;
• and a second conduction terminal to which an off-level direct-current power supply voltage is provided;
• wherein in each unit circuit,
• by the other-stage control signal outputted from a unit circuit of a previous stage going to an on level, the first transistor goes into an on state and the first node goes to an on level,
• thereafter, by the first node going to a stronger on level due to the clock signal provided to the first conduction terminal of the second transistor going to an on level, the third transistor goes into an on state and the on-level direct-current power supply voltage is provided to the second output node,
• thereafter, by the subframe reset signal going to an on level at an end time point of the subframe, the sixth transistor goes into an on state and the off-level direct-current power supply voltage is provided to the second output node,
• the light-emission enable signal is in an on level when the on-level direct-current power supply voltage is provided to the second output node;
• and
• wherein in each subframe,
• the light-emission enable signal having gone to an on level is maintained at the on level until an end time point of the subframe, in all of the plurality of rows, and
• the closer the stage corresponding to the row of the supply destination of the light-emission enable signal is to the final stage of the shift register, the shorter the period during which the light-emission enable signal is maintained at the on level.