Structural descriptions for neurosynaptic networks
AssigneeInternational Business Machines Corporation
InventorDharmendra S. Modha
Life of this patent
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Abstract
Embodiments of the invention provide a method comprising creating a structural description for at least one neurosynaptic core circuit. Each core circuit comprises an interconnect network including plural electronic synapses for interconnecting one or more electronic neurons with one or more electronic axons. The structural description defines a desired neuronal activity for the core circuits. The desired neuronal activity is simulated by programming the core circuits with the structural description. The structural description controls routing of neuronal firing events for the core circuits.
Claims10
A method comprising:
- generating a plurality of modular, reusable, scalable configurations, wherein each configuration comprises information corresponding to a portion of a neural network circuit and indicative of cost of utilizing the configuration to program the corresponding portion, at least one input received by the corresponding portion, at least output generated by the corresponding portion, and at least one function performed by the corresponding portion;
- combining at least two of the configurations to form a complex configuration, wherein the complex configuration comprises a hierarchical arrangement of the at least two configurations;
- and
- programming a multi-core circuit chip structure based on the complex configuration to simulate a plurality of interconnected neurosynaptic core circuits.
A system comprising a computer processor, a computer-readable hardware storage medium, and program code embodied with the computer-readable hardware storage medium for execution by the computer processor to implement a method comprising:
- generating a plurality of modular, reusable, scalable configurations, wherein each configuration comprises information corresponding to a portion of a neural network circuit and indicative of cost of utilizing the configuration to program the corresponding portion, at least one input received by the corresponding portion, at least output generated by the corresponding portion, and at least one function performed by the corresponding portion;
- combining at least two of the configurations to form a complex configuration, wherein the complex configuration comprises a hierarchical arrangement of the at least two configurations;
- and
- programming a multi-core circuit chip structure based on the complex configuration to simulate a plurality of interconnected neurosynaptic core circuits.
A computer program product comprising a computer-readable hardware storage medium having program code embodied therewith, the program code being executable by a computer to implement a method comprising:
- generating a plurality of modular, reusable, scalable configurations, wherein each configuration comprises information corresponding to a portion of a neural network circuit and indicative of cost of utilizing the configuration to program the corresponding portion, at least one input received by the corresponding portion, at least output generated by the corresponding portion, and at least one function performed by the corresponding portion;
- combining at least two of the configurations to form a complex configuration, wherein the complex configuration comprises a hierarchical arrangement of the at least two configurations;
- and
- programming a multi-core circuit chip structure based on the complex configuration to simulate a plurality of interconnected neurosynaptic core circuits.
Dependencies are inferred from the claim text.