Counterfeit microelectronics detection based on capacitive and inductive signatures

A method for detecting an undesirable condition of an integrated circuit comprising:

• providing a testing system including a capacitance measuring system and coupling the testing system to a first integrated circuit comprising at least one power pin for testing;
• commencing taking a plurality of capacitance measurements associated with characterizing capacitive and inductive loading of the at least one power pin wherein each said plurality of capacitance measurements is associated with a different frequency within a specified frequency range comprising a first characterization step and a second characterization step, wherein said first characterization step comprises applying an alternating current signal with a first voltage to the first integrated circuit power pin, wherein said second characterization step comprises sweeping or incrementally modulating or adjusting the alternating current signal across the specified frequency range and taking each of said plurality of capacitance measurements at a plurality of test points in said specified frequency range;
• generating a plurality of first capacitance curve plot data based on said plurality of capacitance measurements and identifying one or more candidate device signature data from said plurality of first capacitance curve plot data comprising at least one of said plurality of capacitance measurements selected associated with at least one resonance transition in said plurality of first capacitance curve plot data or a lack of said resonance transition in said plurality of capacitance curve plot data, wherein said candidate device signature data based on said lack of said resonance transition is determined based on selection of one of said plurality of capacitance measurements within a first segment of said first capacitance curve plot that has a slope value between any at least two data points within said capacitance curve plot data that is closest to a zero slope value, said candidate device signature data comprises capacitance measurement and a respective one of said different frequencies at which said capacitance measurement was taken at;
• selecting one or more device signature data from at least one said candidate device signature data and recording one of said plurality of capacitance measurements associated with said selected candidate device signature data and frequency at which said capacitance measurement was taken for each selected device signature data;
• and
• providing a second integrated circuit having a second power pin and internal electrical circuit manufactured to be a copy of the first integrated circuit, measuring capacitance of said second power pin at said alternating current signal, modulating said alternating current signal based on each said frequency at which said capacitance measurement was taken for each selected device signature data, and measuring capacitance values at each said frequency at which said capacitance measurement was taken for each selected device signature data to produce one or more capacitance comparison data associated with each selected device signature, comparing said one or more capacitance comparison data with a respective said selected device signature data, and determining a match or no match between respective said device signature data and said respective capacitance comparison data to determines if said second integrated circuit is an acceptable or unacceptable part.

A method for detecting an undesirable condition of an integrated circuit comprising:

• providing a testing system including a capacitance measuring system and coupling the testing system to a first integrated circuit comprising at least one power pin for testing;
• commencing taking a plurality of capacitance measurements associated with characterizing capacitive and inductive loading of the power pin where each said measurement is associated with a different frequency within a specified frequency range comprising a first characterization step and a second characterization step, wherein said first characterization step comprises applying an alternating current signal with a first voltage to the power pin, wherein said second characterization step comprises sweeping or incrementally modulating or adjusting the alternating current signal across the specified frequency range and taking each of said plurality of capacitance measurements at a plurality of test points in said specified frequency range;
• generating a plurality of first capacitance curve plot data based on said plurality of capacitance measurements and identifying one or more candidate device signature data from said plurality of first capacitance curve plot data comprising at least one of said plurality of capacitance measurements selected associated with at least one resonance transition in said plurality of first capacitance curve plot data or a lack of said resonance transition in said plurality of capacitance curve plot data, wherein said candidate device signature data based on said lack of said resonance transition is determined based on selection of one of said plurality of capacitance measurements within a first segment of said first capacitance curve plot that has a slope value between any at least two data points within said capacitance curve plot data that is closest to a zero slope value, said candidate device signature data comprises capacitance measurement and a respective one of said different frequencies at which said capacitance measurement was taken at;
• and
• selecting one or more device signature data from at least one said candidate device signature data and recording one of said plurality of capacitance measurements associated with said selected candidate device signature data and frequency at which said capacitance measurement was taken for each selected device signature data.